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//* ----------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//* ----------------------------------------------------------------------------
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//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//* ----------------------------------------------------------------------------
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//* File Name : lib_AT91SAM7S64.h
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//* Object : AT91SAM7S64 inlined functions
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//* Generated : AT91 SW Application Group 08/30/2005 (15:52:59)
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//*
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#include <sys/types.h>
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#include <AT91SAM7.h>
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#include <lib_AT91SAM7.h>
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_ConfigureIt
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//* \brief Interrupt Handler Initialization
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//*----------------------------------------------------------------------------
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unsigned int
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AT91F_AIC_ConfigureIt (unsigned int irq_id, // \arg interrupt number to initialize
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unsigned int priority, // \arg priority to give to the interrupt
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unsigned int src_type, // \arg activation and sense of activation
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THandler handler) // \arg address of the interrupt handler
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{
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unsigned int oldHandler;
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unsigned int mask;
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oldHandler = AT91C_BASE_AIC->AIC_SVR[irq_id];
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mask = 0x1 << irq_id;
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//* Disable the interrupt on the interrupt controller
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AT91C_BASE_AIC->AIC_IDCR = mask;
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//* Save the interrupt handler routine pointer and the interrupt priority
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AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) handler;
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//* Store the Source Mode Register
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AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority;
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//* Clear the interrupt on the interrupt controller
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AT91C_BASE_AIC->AIC_ICCR = mask;
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return (unsigned int) handler;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_SetExceptionVector
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//* \brief Configure vector handler
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//*----------------------------------------------------------------------------
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unsigned int
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AT91F_AIC_SetExceptionVector (unsigned int *pVector, // \arg pointer to the AIC registers
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THandler Handler) // \arg Interrupt Handler
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{
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unsigned int oldVector = *pVector;
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if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
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*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
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else
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*pVector =
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(((((unsigned int) Handler) - ((unsigned int) pVector) -
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0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
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return oldVector;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_Open
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//* \brief Set exception vectors and AIC registers to default values
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//*----------------------------------------------------------------------------
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void
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AT91F_AIC_Open (THandler IrqHandler, // \arg Default IRQ vector exception
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THandler FiqHandler, // \arg Default FIQ vector exception
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THandler DefaultHandler, // \arg Default Handler set in ISR
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THandler SpuriousHandler, // \arg Default Spurious Handler
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unsigned int protectMode) // \arg Debug Control Register
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{
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int i;
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// Disable all interrupts and set IVR to the default handler
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for (i = 0; i < 32; ++i)
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{
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AT91F_AIC_DisableIt (i);
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AT91F_AIC_ConfigureIt (i, AT91C_AIC_PRIOR_LOWEST,
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AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
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}
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// Set the IRQ exception vector
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AT91F_AIC_SetExceptionVector ((unsigned int *) 0x18, IrqHandler);
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// Set the Fast Interrupt exception vector
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AT91F_AIC_SetExceptionVector ((unsigned int *) 0x1C, FiqHandler);
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AT91C_BASE_AIC->AIC_SPU = (unsigned int) SpuriousHandler;
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AT91C_BASE_AIC->AIC_DCR = protectMode;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_Open
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//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
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//*----------------------------------------------------------------------------
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void
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AT91F_PDC_Open (AT91PS_PDC pPDC) // \arg pointer to a PDC controller
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{
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//* Disable the RX and TX PDC transfer requests
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AT91F_PDC_DisableRx (pPDC);
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AT91F_PDC_DisableTx (pPDC);
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//* Reset all Counter register Next buffer first
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AT91F_PDC_SetNextTx (pPDC, NULL, 0);
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AT91F_PDC_SetNextRx (pPDC, NULL, 0);
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AT91F_PDC_SetTx (pPDC, NULL, 0);
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AT91F_PDC_SetRx (pPDC, NULL, 0);
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//* Enable the RX and TX PDC transfer requests
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AT91F_PDC_EnableRx (pPDC);
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AT91F_PDC_EnableTx (pPDC);
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_Close
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//* \brief Close PDC: disable TX and RX reset transfer descriptors
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//*----------------------------------------------------------------------------
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void
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AT91F_PDC_Close (AT91PS_PDC pPDC) // \arg pointer to a PDC controller
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{
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//* Disable the RX and TX PDC transfer requests
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AT91F_PDC_DisableRx (pPDC);
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AT91F_PDC_DisableTx (pPDC);
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//* Reset all Counter register Next buffer first
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AT91F_PDC_SetNextTx (pPDC, NULL, 0);
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AT91F_PDC_SetNextRx (pPDC, NULL, 0);
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AT91F_PDC_SetTx (pPDC, NULL, 0);
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AT91F_PDC_SetRx (pPDC, NULL, 0);
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_SendFrame
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//* \brief Close PDC: disable TX and RX reset transfer descriptors
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//*----------------------------------------------------------------------------
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unsigned int
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AT91F_PDC_SendFrame (AT91PS_PDC pPDC,
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const unsigned char *pBuffer,
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unsigned int szBuffer,
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const unsigned char *pNextBuffer,
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unsigned int szNextBuffer)
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{
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if (AT91F_PDC_IsTxEmpty (pPDC))
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{
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//* Buffer and next buffer can be initialized
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AT91F_PDC_SetTx (pPDC, pBuffer, szBuffer);
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AT91F_PDC_SetNextTx (pPDC, pNextBuffer, szNextBuffer);
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return 2;
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}
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else if (AT91F_PDC_IsNextTxEmpty (pPDC))
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{
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//* Only one buffer can be initialized
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AT91F_PDC_SetNextTx (pPDC, pBuffer, szBuffer);
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return 1;
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}
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else
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{
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//* All buffer are in use...
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return 0;
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}
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_ReceiveFrame
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//* \brief Close PDC: disable TX and RX reset transfer descriptors
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//*----------------------------------------------------------------------------
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unsigned int
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AT91F_PDC_ReceiveFrame (AT91PS_PDC pPDC,
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unsigned char *pBuffer,
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unsigned int szBuffer,
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unsigned char *pNextBuffer, unsigned int szNextBuffer)
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{
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if (AT91F_PDC_IsRxEmpty (pPDC))
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{
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//* Buffer and next buffer can be initialized
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AT91F_PDC_SetRx (pPDC, pBuffer, szBuffer);
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AT91F_PDC_SetNextRx (pPDC, pNextBuffer, szNextBuffer);
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return 2;
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}
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else if (AT91F_PDC_IsNextRxEmpty (pPDC))
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{
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//* Only one buffer can be initialized
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AT91F_PDC_SetNextRx (pPDC, pBuffer, szBuffer);
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return 1;
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}
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else
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{
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//* All buffer are in use...
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return 0;
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}
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}
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//*------------------------------------------------------------------------------
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//* \fn AT91F_PMC_GetMasterClock
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//* \brief Return master clock in Hz which correponds to processor clock for ARM7
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//*------------------------------------------------------------------------------
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unsigned int
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AT91F_PMC_GetMasterClock (AT91PS_PMC pPMC, // \arg pointer to PMC controller
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AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
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unsigned int slowClock) // \arg slowClock in Hz
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{
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unsigned int reg = pPMC->PMC_MCKR;
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unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
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unsigned int pllDivider, pllMultiplier;
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switch (reg & AT91C_PMC_CSS)
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{
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case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
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return slowClock / prescaler;
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case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
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return AT91F_CKGR_GetMainClock (pCKGR, slowClock) / prescaler;
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case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
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reg = pCKGR->CKGR_PLLR;
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pllDivider = (reg & AT91C_CKGR_DIV);
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pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
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return AT91F_CKGR_GetMainClock (pCKGR,
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slowClock) / pllDivider *
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pllMultiplier / prescaler;
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}
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return 0;
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}
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//*--------------------------------------------------------------------------------------
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//* \fn AT91F_RTT_ReadValue()
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//* \brief Read the RTT value
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//*--------------------------------------------------------------------------------------
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unsigned int
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AT91F_RTTReadValue (AT91PS_RTTC pRTTC)
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{
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register volatile unsigned int val1, val2;
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do
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{
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val1 = pRTTC->RTTC_RTVR;
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val2 = pRTTC->RTTC_RTVR;
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}
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while (val1 != val2);
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return (val1);
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}
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250
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251
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//*----------------------------------------------------------------------------
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252
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//* \fn AT91F_SPI_Close
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253
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//* \brief Close SPI: disable IT disable transfert, close PDC
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254
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//*----------------------------------------------------------------------------
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255
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void
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256
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AT91F_SPI_Close (AT91PS_SPI pSPI) // \arg pointer to a SPI controller
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257
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{
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258
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//* Reset all the Chip Select register
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259
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pSPI->SPI_CSR[0] = 0;
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260
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pSPI->SPI_CSR[1] = 0;
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261
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pSPI->SPI_CSR[2] = 0;
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262
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pSPI->SPI_CSR[3] = 0;
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263
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264
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//* Reset the SPI mode
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265
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pSPI->SPI_MR = 0;
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266
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267
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//* Disable all interrupts
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268
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pSPI->SPI_IDR = 0xFFFFFFFF;
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269
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270
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//* Abort the Peripheral Data Transfers
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271
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AT91F_PDC_Close ((AT91PS_PDC) & (pSPI->SPI_RPR));
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272
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273
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//* Disable receiver and transmitter and stop any activity immediately
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274
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pSPI->SPI_CR = AT91C_SPI_SPIDIS;
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275
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}
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276
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277
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//*----------------------------------------------------------------------------
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278
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//* \fn AT91F_ADC_CfgTimings
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279
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//* \brief Configure the different necessary timings of the ADC controller
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280
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//*----------------------------------------------------------------------------
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281
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void
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282
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AT91F_ADC_CfgTimings (AT91PS_ADC pADC, // pointer to a ADC controller
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283
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unsigned int mck_clock, // in MHz
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284
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unsigned int adc_clock, // in MHz
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285
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unsigned int startup_time, // in us
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286
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unsigned int sample_and_hold_time) // in ns
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287
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{
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288
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unsigned int prescal, startup, shtim;
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289
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290
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prescal = mck_clock / (2 * adc_clock) - 1;
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291
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startup = adc_clock * startup_time / 8 - 1;
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292
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shtim = adc_clock * sample_and_hold_time / 1000 - 1;
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293
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294
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//* Write to the MR register
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295
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pADC->ADC_MR =
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296
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((prescal << 8) & AT91C_ADC_PRESCAL) | ((startup << 16) &
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297
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AT91C_ADC_STARTUP) | ((shtim <<
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298
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24) &
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299
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AT91C_ADC_SHTIM);
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300
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}
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301
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302
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//*----------------------------------------------------------------------------
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303
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//* \fn AT91F_SSC_SetBaudrate
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304
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//* \brief Set the baudrate according to the CPU clock
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305
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//*----------------------------------------------------------------------------
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306
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void
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307
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AT91F_SSC_SetBaudrate (AT91PS_SSC pSSC, // \arg pointer to a SSC controller
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308
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unsigned int mainClock, // \arg peripheral clock
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309
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unsigned int speed) // \arg SSC baudrate
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310
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{
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311
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unsigned int baud_value;
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312
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//* Define the baud rate divisor register
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313
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if (speed == 0)
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314
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baud_value = 0;
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315
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else
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316
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{
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317
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baud_value = (unsigned int) (mainClock * 10) / (2 * speed);
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318
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if ((baud_value % 10) >= 5)
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319
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baud_value = (baud_value / 10) + 1;
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320
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else
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321
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baud_value /= 10;
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322
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}
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323
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324
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pSSC->SSC_CMR = baud_value;
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325
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}
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326
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|
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327
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//*----------------------------------------------------------------------------
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328
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//* \fn AT91F_SSC_Configure
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329
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//* \brief Configure SSC
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330
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//*----------------------------------------------------------------------------
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331
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void
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332
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AT91F_SSC_Configure (AT91PS_SSC pSSC, // \arg pointer to a SSC controller
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333
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unsigned int syst_clock, // \arg System Clock Frequency
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334
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unsigned int baud_rate, // \arg Expected Baud Rate Frequency
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335
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unsigned int clock_rx, // \arg Receiver Clock Parameters
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336
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unsigned int mode_rx, // \arg mode Register to be programmed
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337
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unsigned int clock_tx, // \arg Transmitter Clock Parameters
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338
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unsigned int mode_tx) // \arg mode Register to be programmed
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|
339
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{
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340
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//* Disable interrupts
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341
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pSSC->SSC_IDR = (unsigned int) -1;
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342
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343
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//* Reset receiver and transmitter
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344
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pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
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|
345
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|
|
346
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//* Define the Clock Mode Register
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347
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AT91F_SSC_SetBaudrate (pSSC, syst_clock, baud_rate);
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348
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349
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//* Write the Receive Clock Mode Register
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350
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pSSC->SSC_RCMR = clock_rx;
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|
351
|
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352
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//* Write the Transmit Clock Mode Register
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353
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pSSC->SSC_TCMR = clock_tx;
|
|
354
|
|
|
355
|
//* Write the Receive Frame Mode Register
|
|
356
|
pSSC->SSC_RFMR = mode_rx;
|
|
357
|
|
|
358
|
//* Write the Transmit Frame Mode Register
|
|
359
|
pSSC->SSC_TFMR = mode_tx;
|
|
360
|
|
|
361
|
//* Clear Transmit and Receive Counters
|
|
362
|
AT91F_PDC_Open ((AT91PS_PDC) & (pSSC->SSC_RPR));
|
|
363
|
|
|
364
|
|
|
365
|
}
|
|
366
|
|
|
367
|
//*----------------------------------------------------------------------------
|
|
368
|
//* \fn AT91F_US_Configure
|
|
369
|
//* \brief Configure USART
|
|
370
|
//*----------------------------------------------------------------------------
|
|
371
|
void
|
|
372
|
AT91F_US_Configure (AT91PS_USART pUSART, // \arg pointer to a USART controller
|
|
373
|
unsigned int mainClock, // \arg peripheral clock
|
|
374
|
unsigned int mode, // \arg mode Register to be programmed
|
|
375
|
unsigned int baudRate, // \arg baudrate to be programmed
|
|
376
|
unsigned int timeguard) // \arg timeguard to be programmed
|
|
377
|
{
|
|
378
|
//* Disable interrupts
|
|
379
|
pUSART->US_IDR = (unsigned int) -1;
|
|
380
|
|
|
381
|
//* Reset receiver and transmitter
|
|
382
|
pUSART->US_CR =
|
|
383
|
AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
|
|
384
|
|
|
385
|
//* Define the baud rate divisor register
|
|
386
|
AT91F_US_SetBaudrate (pUSART, mainClock, baudRate);
|
|
387
|
|
|
388
|
//* Write the Timeguard Register
|
|
389
|
AT91F_US_SetTimeguard (pUSART, timeguard);
|
|
390
|
|
|
391
|
//* Clear Transmit and Receive Counters
|
|
392
|
AT91F_PDC_Open ((AT91PS_PDC) & (pUSART->US_RPR));
|
|
393
|
|
|
394
|
//* Define the USART mode
|
|
395
|
pUSART->US_MR = mode;
|
|
396
|
|
|
397
|
}
|
|
398
|
|
|
399
|
//*----------------------------------------------------------------------------
|
|
400
|
//* \fn AT91F_US_Close
|
|
401
|
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
|
|
402
|
//*----------------------------------------------------------------------------
|
|
403
|
void
|
|
404
|
AT91F_US_Close (AT91PS_USART pUSART) // \arg pointer to a USART controller
|
|
405
|
{
|
|
406
|
//* Reset the baud rate divisor register
|
|
407
|
pUSART->US_BRGR = 0;
|
|
408
|
|
|
409
|
//* Reset the USART mode
|
|
410
|
pUSART->US_MR = 0;
|
|
411
|
|
|
412
|
//* Reset the Timeguard Register
|
|
413
|
pUSART->US_TTGR = 0;
|
|
414
|
|
|
415
|
//* Disable all interrupts
|
|
416
|
pUSART->US_IDR = 0xFFFFFFFF;
|
|
417
|
|
|
418
|
//* Abort the Peripheral Data Transfers
|
|
419
|
AT91F_PDC_Close ((AT91PS_PDC) & (pUSART->US_RPR));
|
|
420
|
|
|
421
|
//* Disable receiver and transmitter and stop any activity immediately
|
|
422
|
pUSART->US_CR =
|
|
423
|
AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
|
|
424
|
}
|
