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//  ----------------------------------------------------------------------------

//          ATMEL Microcontroller Software Support  -  ROUSSET  -

//  ----------------------------------------------------------------------------

//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR

//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE

//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,

//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,

//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

//  ----------------------------------------------------------------------------

// File Name           : AT91SAM7S64.h

// Object              : AT91SAM7S64 definitions

// Generated           : AT91 SW Application Group  08/30/2005 (15:52:59)

// 

// CVS Reference       : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005//

// CVS Reference       : /SYS_SAM7S.pl/1.2/Tue Feb  1 17:01:52 2005//

// CVS Reference       : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005//

// CVS Reference       : /PMC_SAM7S_USB.pl/1.4/Tue Feb  8 13:58:22 2005//

// CVS Reference       : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005//

// CVS Reference       : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005//

// CVS Reference       : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005//

// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//

// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//

// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//

// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//

// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//

// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//

// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//

// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//

// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//

// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//

// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//

// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//

// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//

// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//

//  ----------------------------------------------------------------------------

#ifndef __AT91SAM7_H__

#define __AT91SAM7_H__

typedef volatile unsigned int AT91_REG;	// Hardware register definition

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR System Peripherals

// *****************************************************************************

typedef struct _AT91S_SYS

{

  AT91_REG AIC_SMR[32];		// Source Mode Register

  AT91_REG AIC_SVR[32];		// Source Vector Register

  AT91_REG AIC_IVR;		// IRQ Vector Register

  AT91_REG AIC_FVR;		// FIQ Vector Register

  AT91_REG AIC_ISR;		// Interrupt Status Register

  AT91_REG AIC_IPR;		// Interrupt Pending Register

  AT91_REG AIC_IMR;		// Interrupt Mask Register

  AT91_REG AIC_CISR;		// Core Interrupt Status Register

  AT91_REG Reserved0[2];	// 

  AT91_REG AIC_IECR;		// Interrupt Enable Command Register

  AT91_REG AIC_IDCR;		// Interrupt Disable Command Register

  AT91_REG AIC_ICCR;		// Interrupt Clear Command Register

  AT91_REG AIC_ISCR;		// Interrupt Set Command Register

  AT91_REG AIC_EOICR;		// End of Interrupt Command Register

  AT91_REG AIC_SPU;		// Spurious Vector Register

  AT91_REG AIC_DCR;		// Debug Control Register (Protect)

  AT91_REG Reserved1[1];	// 

  AT91_REG AIC_FFER;		// Fast Forcing Enable Register

  AT91_REG AIC_FFDR;		// Fast Forcing Disable Register

  AT91_REG AIC_FFSR;		// Fast Forcing Status Register

  AT91_REG Reserved2[45];	// 

  AT91_REG DBGU_CR;		// Control Register

  AT91_REG DBGU_MR;		// Mode Register

  AT91_REG DBGU_IER;		// Interrupt Enable Register

  AT91_REG DBGU_IDR;		// Interrupt Disable Register

  AT91_REG DBGU_IMR;		// Interrupt Mask Register

  AT91_REG DBGU_CSR;		// Channel Status Register

  AT91_REG DBGU_RHR;		// Receiver Holding Register

  AT91_REG DBGU_THR;		// Transmitter Holding Register

  AT91_REG DBGU_BRGR;		// Baud Rate Generator Register

  AT91_REG Reserved3[7];	// 

  AT91_REG DBGU_CIDR;		// Chip ID Register

  AT91_REG DBGU_EXID;		// Chip ID Extension Register

  AT91_REG DBGU_FNTR;		// Force NTRST Register

  AT91_REG Reserved4[45];	// 

  AT91_REG DBGU_RPR;		// Receive Pointer Register

  AT91_REG DBGU_RCR;		// Receive Counter Register

  AT91_REG DBGU_TPR;		// Transmit Pointer Register

  AT91_REG DBGU_TCR;		// Transmit Counter Register

  AT91_REG DBGU_RNPR;		// Receive Next Pointer Register

  AT91_REG DBGU_RNCR;		// Receive Next Counter Register

  AT91_REG DBGU_TNPR;		// Transmit Next Pointer Register

  AT91_REG DBGU_TNCR;		// Transmit Next Counter Register

  AT91_REG DBGU_PTCR;		// PDC Transfer Control Register

  AT91_REG DBGU_PTSR;		// PDC Transfer Status Register

  AT91_REG Reserved5[54];	// 

  AT91_REG PIOA_PER;		// PIO Enable Register

  AT91_REG PIOA_PDR;		// PIO Disable Register

  AT91_REG PIOA_PSR;		// PIO Status Register

  AT91_REG Reserved6[1];	// 

  AT91_REG PIOA_OER;		// Output Enable Register

  AT91_REG PIOA_ODR;		// Output Disable Registerr

  AT91_REG PIOA_OSR;		// Output Status Register

  AT91_REG Reserved7[1];	// 

  AT91_REG PIOA_IFER;		// Input Filter Enable Register

  AT91_REG PIOA_IFDR;		// Input Filter Disable Register

  AT91_REG PIOA_IFSR;		// Input Filter Status Register

  AT91_REG Reserved8[1];	// 

  AT91_REG PIOA_SODR;		// Set Output Data Register

  AT91_REG PIOA_CODR;		// Clear Output Data Register

  AT91_REG PIOA_ODSR;		// Output Data Status Register

  AT91_REG PIOA_PDSR;		// Pin Data Status Register

  AT91_REG PIOA_IER;		// Interrupt Enable Register

  AT91_REG PIOA_IDR;		// Interrupt Disable Register

  AT91_REG PIOA_IMR;		// Interrupt Mask Register

  AT91_REG PIOA_ISR;		// Interrupt Status Register

  AT91_REG PIOA_MDER;		// Multi-driver Enable Register

  AT91_REG PIOA_MDDR;		// Multi-driver Disable Register

  AT91_REG PIOA_MDSR;		// Multi-driver Status Register

  AT91_REG Reserved9[1];	// 

  AT91_REG PIOA_PPUDR;		// Pull-up Disable Register

  AT91_REG PIOA_PPUER;		// Pull-up Enable Register

  AT91_REG PIOA_PPUSR;		// Pull-up Status Register

  AT91_REG Reserved10[1];	// 

  AT91_REG PIOA_ASR;		// Select A Register

  AT91_REG PIOA_BSR;		// Select B Register

  AT91_REG PIOA_ABSR;		// AB Select Status Register

  AT91_REG Reserved11[9];	// 

  AT91_REG PIOA_OWER;		// Output Write Enable Register

  AT91_REG PIOA_OWDR;		// Output Write Disable Register

  AT91_REG PIOA_OWSR;		// Output Write Status Register

  AT91_REG Reserved12[469];	// 

  AT91_REG PMC_SCER;		// System Clock Enable Register

  AT91_REG PMC_SCDR;		// System Clock Disable Register

  AT91_REG PMC_SCSR;		// System Clock Status Register

  AT91_REG Reserved13[1];	// 

  AT91_REG PMC_PCER;		// Peripheral Clock Enable Register

  AT91_REG PMC_PCDR;		// Peripheral Clock Disable Register

  AT91_REG PMC_PCSR;		// Peripheral Clock Status Register

  AT91_REG Reserved14[1];	// 

  AT91_REG PMC_MOR;		// Main Oscillator Register

  AT91_REG PMC_MCFR;		// Main Clock  Frequency Register

  AT91_REG Reserved15[1];	// 

  AT91_REG PMC_PLLR;		// PLL Register

  AT91_REG PMC_MCKR;		// Master Clock Register

  AT91_REG Reserved16[3];	// 

  AT91_REG PMC_PCKR[3];		// Programmable Clock Register

  AT91_REG Reserved17[5];	// 

  AT91_REG PMC_IER;		// Interrupt Enable Register

  AT91_REG PMC_IDR;		// Interrupt Disable Register

  AT91_REG PMC_SR;		// Status Register

  AT91_REG PMC_IMR;		// Interrupt Mask Register

  AT91_REG Reserved18[36];	// 

  AT91_REG RSTC_RCR;		// Reset Control Register

  AT91_REG RSTC_RSR;		// Reset Status Register

  AT91_REG RSTC_RMR;		// Reset Mode Register

  AT91_REG Reserved19[5];	// 

  AT91_REG RTTC_RTMR;		// Real-time Mode Register

  AT91_REG RTTC_RTAR;		// Real-time Alarm Register

  AT91_REG RTTC_RTVR;		// Real-time Value Register

  AT91_REG RTTC_RTSR;		// Real-time Status Register

  AT91_REG PITC_PIMR;		// Period Interval Mode Register

  AT91_REG PITC_PISR;		// Period Interval Status Register

  AT91_REG PITC_PIVR;		// Period Interval Value Register

  AT91_REG PITC_PIIR;		// Period Interval Image Register

  AT91_REG WDTC_WDCR;		// Watchdog Control Register

  AT91_REG WDTC_WDMR;		// Watchdog Mode Register

  AT91_REG WDTC_WDSR;		// Watchdog Status Register

  AT91_REG Reserved20[5];	// 

  AT91_REG VREG_MR;		// Voltage Regulator Mode Register

} AT91S_SYS, *AT91PS_SYS;

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller

// *****************************************************************************

typedef struct _AT91S_AIC

{

  AT91_REG AIC_SMR[32];		// Source Mode Register

  AT91_REG AIC_SVR[32];		// Source Vector Register

  AT91_REG AIC_IVR;		// IRQ Vector Register

  AT91_REG AIC_FVR;		// FIQ Vector Register

  AT91_REG AIC_ISR;		// Interrupt Status Register

  AT91_REG AIC_IPR;		// Interrupt Pending Register

  AT91_REG AIC_IMR;		// Interrupt Mask Register

  AT91_REG AIC_CISR;		// Core Interrupt Status Register

  AT91_REG Reserved0[2];	// 

  AT91_REG AIC_IECR;		// Interrupt Enable Command Register

  AT91_REG AIC_IDCR;		// Interrupt Disable Command Register

  AT91_REG AIC_ICCR;		// Interrupt Clear Command Register

  AT91_REG AIC_ISCR;		// Interrupt Set Command Register

  AT91_REG AIC_EOICR;		// End of Interrupt Command Register

  AT91_REG AIC_SPU;		// Spurious Vector Register

  AT91_REG AIC_DCR;		// Debug Control Register (Protect)

  AT91_REG Reserved1[1];	// 

  AT91_REG AIC_FFER;		// Fast Forcing Enable Register

  AT91_REG AIC_FFDR;		// Fast Forcing Disable Register

  AT91_REG AIC_FFSR;		// Fast Forcing Status Register

} AT91S_AIC, *AT91PS_AIC;

// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 

#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0)	// (AIC) Priority Level

#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0)	// (AIC) Lowest priority level

#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7)	// (AIC) Highest priority level

#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5)	// (AIC) Interrupt Source Type

#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5)	// (AIC) Internal Sources Code Label High-level Sensitive

#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5)	// (AIC) External Sources Code Label Low-level Sensitive

#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5)	// (AIC) Internal Sources Code Label Positive Edge triggered

#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5)	// (AIC) External Sources Code Label Negative Edge triggered

#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5)	// (AIC) Internal Or External Sources Code Label High-level Sensitive

#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5)	// (AIC) Internal Or External Sources Code Label Positive Edge triggered

// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 

#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0)	// (AIC) NFIQ Status

#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1)	// (AIC) NIRQ Status

// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 

#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0)	// (AIC) Protection Mode

#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1)	// (AIC) General Mask

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller

// *****************************************************************************

typedef struct _AT91S_PDC

{

  AT91_REG PDC_RPR;		// Receive Pointer Register

  AT91_REG PDC_RCR;		// Receive Counter Register

  AT91_REG PDC_TPR;		// Transmit Pointer Register

  AT91_REG PDC_TCR;		// Transmit Counter Register

  AT91_REG PDC_RNPR;		// Receive Next Pointer Register

  AT91_REG PDC_RNCR;		// Receive Next Counter Register

  AT91_REG PDC_TNPR;		// Transmit Next Pointer Register

  AT91_REG PDC_TNCR;		// Transmit Next Counter Register

  AT91_REG PDC_PTCR;		// PDC Transfer Control Register

  AT91_REG PDC_PTSR;		// PDC Transfer Status Register

} AT91S_PDC, *AT91PS_PDC;

// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 

#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0)	// (PDC) Receiver Transfer Enable

#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1)	// (PDC) Receiver Transfer Disable

#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8)	// (PDC) Transmitter Transfer Enable

#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9)	// (PDC) Transmitter Transfer Disable

// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Debug Unit

// *****************************************************************************

typedef struct _AT91S_DBGU

{

  AT91_REG DBGU_CR;		// Control Register

  AT91_REG DBGU_MR;		// Mode Register

  AT91_REG DBGU_IER;		// Interrupt Enable Register

  AT91_REG DBGU_IDR;		// Interrupt Disable Register

  AT91_REG DBGU_IMR;		// Interrupt Mask Register

  AT91_REG DBGU_CSR;		// Channel Status Register

  AT91_REG DBGU_RHR;		// Receiver Holding Register

  AT91_REG DBGU_THR;		// Transmitter Holding Register

  AT91_REG DBGU_BRGR;		// Baud Rate Generator Register

  AT91_REG Reserved0[7];	// 

  AT91_REG DBGU_CIDR;		// Chip ID Register

  AT91_REG DBGU_EXID;		// Chip ID Extension Register

  AT91_REG DBGU_FNTR;		// Force NTRST Register

  AT91_REG Reserved1[45];	// 

  AT91_REG DBGU_RPR;		// Receive Pointer Register

  AT91_REG DBGU_RCR;		// Receive Counter Register

  AT91_REG DBGU_TPR;		// Transmit Pointer Register

  AT91_REG DBGU_TCR;		// Transmit Counter Register

  AT91_REG DBGU_RNPR;		// Receive Next Pointer Register

  AT91_REG DBGU_RNCR;		// Receive Next Counter Register

  AT91_REG DBGU_TNPR;		// Transmit Next Pointer Register

  AT91_REG DBGU_TNCR;		// Transmit Next Counter Register

  AT91_REG DBGU_PTCR;		// PDC Transfer Control Register

  AT91_REG DBGU_PTSR;		// PDC Transfer Status Register

} AT91S_DBGU, *AT91PS_DBGU;

// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 

#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2)	// (DBGU) Reset Receiver

#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3)	// (DBGU) Reset Transmitter

#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4)	// (DBGU) Receiver Enable

#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5)	// (DBGU) Receiver Disable

#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6)	// (DBGU) Transmitter Enable

#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7)	// (DBGU) Transmitter Disable

#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8)	// (DBGU) Reset Status Bits

// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 

#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9)	// (DBGU) Parity type

#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9)	// (DBGU) Even Parity

#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9)	// (DBGU) Odd Parity

#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9)	// (DBGU) Parity forced to 0 (Space)

#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9)	// (DBGU) Parity forced to 1 (Mark)

#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9)	// (DBGU) No Parity

#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9)	// (DBGU) Multi-drop mode

#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14)	// (DBGU) Channel Mode

#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14)	// (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.

#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14)	// (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.

#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14)	// (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.

#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14)	// (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.

// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 

#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0)	// (DBGU) RXRDY Interrupt

#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1)	// (DBGU) TXRDY Interrupt

#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3)	// (DBGU) End of Receive Transfer Interrupt

#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4)	// (DBGU) End of Transmit Interrupt

#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5)	// (DBGU) Overrun Interrupt

#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6)	// (DBGU) Framing Error Interrupt

#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7)	// (DBGU) Parity Error Interrupt

#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9)	// (DBGU) TXEMPTY Interrupt

#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11)	// (DBGU) TXBUFE Interrupt

#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12)	// (DBGU) RXBUFF Interrupt

#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30)	// (DBGU) COMM_TX Interrupt

#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31)	// (DBGU) COMM_RX Interrupt

// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 

// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 

// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 

// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 

#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0)	// (DBGU) Force NTRST in JTAG

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler

// *****************************************************************************

typedef struct _AT91S_PIO

{

  AT91_REG PIO_PER;		// PIO Enable Register

  AT91_REG PIO_PDR;		// PIO Disable Register

  AT91_REG PIO_PSR;		// PIO Status Register

  AT91_REG Reserved0[1];	// 

  AT91_REG PIO_OER;		// Output Enable Register

  AT91_REG PIO_ODR;		// Output Disable Registerr

  AT91_REG PIO_OSR;		// Output Status Register

  AT91_REG Reserved1[1];	// 

  AT91_REG PIO_IFER;		// Input Filter Enable Register

  AT91_REG PIO_IFDR;		// Input Filter Disable Register

  AT91_REG PIO_IFSR;		// Input Filter Status Register

  AT91_REG Reserved2[1];	// 

  AT91_REG PIO_SODR;		// Set Output Data Register

  AT91_REG PIO_CODR;		// Clear Output Data Register

  AT91_REG PIO_ODSR;		// Output Data Status Register

  AT91_REG PIO_PDSR;		// Pin Data Status Register

  AT91_REG PIO_IER;		// Interrupt Enable Register

  AT91_REG PIO_IDR;		// Interrupt Disable Register

  AT91_REG PIO_IMR;		// Interrupt Mask Register

  AT91_REG PIO_ISR;		// Interrupt Status Register

  AT91_REG PIO_MDER;		// Multi-driver Enable Register

  AT91_REG PIO_MDDR;		// Multi-driver Disable Register

  AT91_REG PIO_MDSR;		// Multi-driver Status Register

  AT91_REG Reserved3[1];	// 

  AT91_REG PIO_PPUDR;		// Pull-up Disable Register

  AT91_REG PIO_PPUER;		// Pull-up Enable Register

  AT91_REG PIO_PPUSR;		// Pull-up Status Register

  AT91_REG Reserved4[1];	// 

  AT91_REG PIO_ASR;		// Select A Register

  AT91_REG PIO_BSR;		// Select B Register

  AT91_REG PIO_ABSR;		// AB Select Status Register

  AT91_REG Reserved5[9];	// 

  AT91_REG PIO_OWER;		// Output Write Enable Register

  AT91_REG PIO_OWDR;		// Output Write Disable Register

  AT91_REG PIO_OWSR;		// Output Write Status Register

} AT91S_PIO, *AT91PS_PIO;

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Clock Generator Controler

// *****************************************************************************

typedef struct _AT91S_CKGR

{

  AT91_REG CKGR_MOR;		// Main Oscillator Register

  AT91_REG CKGR_MCFR;		// Main Clock  Frequency Register

  AT91_REG Reserved0[1];	// 

  AT91_REG CKGR_PLLR;		// PLL Register

} AT91S_CKGR, *AT91PS_CKGR;

// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 

#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0)	// (CKGR) Main Oscillator Enable

#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1)	// (CKGR) Main Oscillator Bypass

#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8)	// (CKGR) Main Oscillator Start-up Time

// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 

#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0)	// (CKGR) Main Clock Frequency

#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16)	// (CKGR) Main Clock Ready

// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 

#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0)	// (CKGR) Divider Selected

#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0)	// (CKGR) Divider output is 0

#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1)	// (CKGR) Divider is bypassed

#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8)	// (CKGR) PLL Counter

#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14)	// (CKGR) PLL Output Frequency Range

#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14)	// (CKGR) Please refer to the PLL datasheet

#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14)	// (CKGR) Please refer to the PLL datasheet

#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14)	// (CKGR) Please refer to the PLL datasheet

#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14)	// (CKGR) Please refer to the PLL datasheet

#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16)	// (CKGR) PLL Multiplier

#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28)	// (CKGR) Divider for USB Clocks

#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28)	// (CKGR) Divider output is PLL clock output

#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28)	// (CKGR) Divider output is PLL clock output divided by 2

#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28)	// (CKGR) Divider output is PLL clock output divided by 4

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Power Management Controler

// *****************************************************************************

typedef struct _AT91S_PMC

{

  AT91_REG PMC_SCER;		// System Clock Enable Register

  AT91_REG PMC_SCDR;		// System Clock Disable Register

  AT91_REG PMC_SCSR;		// System Clock Status Register

  AT91_REG Reserved0[1];	// 

  AT91_REG PMC_PCER;		// Peripheral Clock Enable Register

  AT91_REG PMC_PCDR;		// Peripheral Clock Disable Register

  AT91_REG PMC_PCSR;		// Peripheral Clock Status Register

  AT91_REG Reserved1[1];	// 

  AT91_REG PMC_MOR;		// Main Oscillator Register

  AT91_REG PMC_MCFR;		// Main Clock  Frequency Register

  AT91_REG Reserved2[1];	// 

  AT91_REG PMC_PLLR;		// PLL Register

  AT91_REG PMC_MCKR;		// Master Clock Register

  AT91_REG Reserved3[3];	// 

  AT91_REG PMC_PCKR[3];		// Programmable Clock Register

  AT91_REG Reserved4[5];	// 

  AT91_REG PMC_IER;		// Interrupt Enable Register

  AT91_REG PMC_IDR;		// Interrupt Disable Register

  AT91_REG PMC_SR;		// Status Register

  AT91_REG PMC_IMR;		// Interrupt Mask Register

} AT91S_PMC, *AT91PS_PMC;

// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 

#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0)	// (PMC) Processor Clock

#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7)	// (PMC) USB Device Port Clock

#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8)	// (PMC) Programmable Clock Output

#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9)	// (PMC) Programmable Clock Output

#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10)	// (PMC) Programmable Clock Output

// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 

// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 

// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 

// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 

// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 

// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 

#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0)	// (PMC) Programmable Clock Selection

#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0)	// (PMC) Slow Clock is selected

#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1)	// (PMC) Main Clock is selected

#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3)	// (PMC) Clock from PLL is selected

#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2)	// (PMC) Programmable Clock Prescaler

#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2)	// (PMC) Selected clock

#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2)	// (PMC) Selected clock divided by 2

#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2)	// (PMC) Selected clock divided by 4

#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2)	// (PMC) Selected clock divided by 8

#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2)	// (PMC) Selected clock divided by 16

#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2)	// (PMC) Selected clock divided by 32

#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2)	// (PMC) Selected clock divided by 64

// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 

// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 

#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0)	// (PMC) MOSC Status/Enable/Disable/Mask

#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2)	// (PMC) PLL Status/Enable/Disable/Mask

#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3)	// (PMC) MCK_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8)	// (PMC) PCK0_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9)	// (PMC) PCK1_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10)	// (PMC) PCK2_RDY Status/Enable/Disable/Mask

// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 

// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 

// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Reset Controller Interface

// *****************************************************************************

typedef struct _AT91S_RSTC

{

  AT91_REG RSTC_RCR;		// Reset Control Register

  AT91_REG RSTC_RSR;		// Reset Status Register

  AT91_REG RSTC_RMR;		// Reset Mode Register

} AT91S_RSTC, *AT91PS_RSTC;

// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 

#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0)	// (RSTC) Processor Reset

#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2)	// (RSTC) Peripheral Reset

#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3)	// (RSTC) External Reset

#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24)	// (RSTC) Password

// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 

#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0)	// (RSTC) User Reset Status

#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1)	// (RSTC) Brownout Detection Status

#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8)	// (RSTC) Reset Type

#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8)	// (RSTC) Power-up Reset. VDDCORE rising.

#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8)	// (RSTC) WakeUp Reset. VDDCORE rising.

#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8)	// (RSTC) Watchdog Reset. Watchdog overflow occured.

#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8)	// (RSTC) Software Reset. Processor reset required by the software.

#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8)	// (RSTC) User Reset. NRST pin detected low.

#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8)	// (RSTC) Brownout Reset occured.

#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16)	// (RSTC) NRST pin level

#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17)	// (RSTC) Software Reset Command in Progress.

// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 

#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0)	// (RSTC) User Reset Enable

#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4)	// (RSTC) User Reset Interrupt Enable

#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8)	// (RSTC) User Reset Length

#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16)	// (RSTC) Brownout Detection Interrupt Enable

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface

// *****************************************************************************

typedef struct _AT91S_RTTC

{

  AT91_REG RTTC_RTMR;		// Real-time Mode Register

  AT91_REG RTTC_RTAR;		// Real-time Alarm Register

  AT91_REG RTTC_RTVR;		// Real-time Value Register

  AT91_REG RTTC_RTSR;		// Real-time Status Register

} AT91S_RTTC, *AT91PS_RTTC;

// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 

#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0)	// (RTTC) Real-time Timer Prescaler Value

#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16)	// (RTTC) Alarm Interrupt Enable

#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17)	// (RTTC) Real Time Timer Increment Interrupt Enable

#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18)	// (RTTC) Real Time Timer Restart

// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 

#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0)	// (RTTC) Alarm Value

// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 

#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0)	// (RTTC) Current Real-time Value

// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 

#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0)	// (RTTC) Real-time Alarm Status

#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1)	// (RTTC) Real-time Timer Increment

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface

// *****************************************************************************

typedef struct _AT91S_PITC

{

  AT91_REG PITC_PIMR;		// Period Interval Mode Register

  AT91_REG PITC_PISR;		// Period Interval Status Register

  AT91_REG PITC_PIVR;		// Period Interval Value Register

  AT91_REG PITC_PIIR;		// Period Interval Image Register

} AT91S_PITC, *AT91PS_PITC;

// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 

#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0)	// (PITC) Periodic Interval Value

#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24)	// (PITC) Periodic Interval Timer Enabled

#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25)	// (PITC) Periodic Interval Timer Interrupt Enable

// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 

#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0)	// (PITC) Periodic Interval Timer Status

// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 

#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0)	// (PITC) Current Periodic Interval Value

#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20)	// (PITC) Periodic Interval Counter

// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface

// *****************************************************************************

typedef struct _AT91S_WDTC

{

  AT91_REG WDTC_WDCR;		// Watchdog Control Register

  AT91_REG WDTC_WDMR;		// Watchdog Mode Register

  AT91_REG WDTC_WDSR;		// Watchdog Status Register

} AT91S_WDTC, *AT91PS_WDTC;

// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 

#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0)	// (WDTC) Watchdog Restart

#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24)	// (WDTC) Watchdog KEY Password

// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 

#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0)	// (WDTC) Watchdog Timer Restart

#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12)	// (WDTC) Watchdog Fault Interrupt Enable

#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13)	// (WDTC) Watchdog Reset Enable

#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14)	// (WDTC) Watchdog Timer Restart

#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15)	// (WDTC) Watchdog Disable

#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16)	// (WDTC) Watchdog Delta Value

#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28)	// (WDTC) Watchdog Debug Halt

#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29)	// (WDTC) Watchdog Idle Halt

// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 

#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0)	// (WDTC) Watchdog Underflow

#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1)	// (WDTC) Watchdog Error

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface

// *****************************************************************************

typedef struct _AT91S_VREG

{

  AT91_REG VREG_MR;		// Voltage Regulator Mode Register

} AT91S_VREG, *AT91PS_VREG;

// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 

#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0)	// (VREG) Voltage Regulator Power Standby Mode

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Memory Controller Interface

// *****************************************************************************

typedef struct _AT91S_MC

{

  AT91_REG MC_RCR;		// MC Remap Control Register

  AT91_REG MC_ASR;		// MC Abort Status Register

  AT91_REG MC_AASR;		// MC Abort Address Status Register

  AT91_REG Reserved0[21];	// 

  AT91_REG MC_FMR;		// MC Flash Mode Register

  AT91_REG MC_FCR;		// MC Flash Command Register

  AT91_REG MC_FSR;		// MC Flash Status Register

} AT91S_MC, *AT91PS_MC;

// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 

#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0)	// (MC) Remap Command Bit

// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 

#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0)	// (MC) Undefined Addess Abort Status

#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1)	// (MC) Misaligned Addess Abort Status

#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8)	// (MC) Abort Size Status

#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8)	// (MC) Byte

#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8)	// (MC) Half-word

#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8)	// (MC) Word

#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10)	// (MC) Abort Type Status

#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10)	// (MC) Data Read

#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10)	// (MC) Data Write

#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10)	// (MC) Code Fetch

#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16)	// (MC) Master 0 Abort Source

#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17)	// (MC) Master 1 Abort Source

#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24)	// (MC) Saved Master 0 Abort Source

#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25)	// (MC) Saved Master 1 Abort Source

// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 

#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0)	// (MC) Flash Ready

#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2)	// (MC) Lock Error

#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3)	// (MC) Programming Error

#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7)	// (MC) No Erase Before Programming

#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8)	// (MC) Flash Wait State

#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8)	// (MC) 1 cycle for Read, 2 for Write operations

#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8)	// (MC) 2 cycles for Read, 3 for Write operations

#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8)	// (MC) 3 cycles for Read, 4 for Write operations

#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8)	// (MC) 4 cycles for Read, 4 for Write operations

#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16)	// (MC) Flash Microsecond Cycle Number

// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 

#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0)	// (MC) Flash Command

#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1)	// (MC) Starts the programming of th epage specified by PAGEN.

#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2)	// (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.

#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3)	// (MC) The lock sequence automatically happens after the programming sequence is completed.

#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4)	// (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.

#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8)	// (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.

#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB)	// (MC) Set General Purpose NVM bits.

#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD)	// (MC) Clear General Purpose NVM bits.

#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF)	// (MC) Set Security Bit.

#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8)	// (MC) Page Number

#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24)	// (MC) Writing Protect Key

// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 

#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4)	// (MC) Security Bit Status

#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8)	// (MC) Sector 0 Lock Status

#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9)	// (MC) Sector 1 Lock Status

#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10)	// (MC) Sector 2 Lock Status

#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11)	// (MC) Sector 3 Lock Status

#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12)	// (MC) Sector 4 Lock Status

#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13)	// (MC) Sector 5 Lock Status

#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14)	// (MC) Sector 6 Lock Status

#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15)	// (MC) Sector 7 Lock Status

#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16)	// (MC) Sector 0 Lock Status

#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17)	// (MC) Sector 1 Lock Status

#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18)	// (MC) Sector 2 Lock Status

#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19)	// (MC) Sector 3 Lock Status

#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20)	// (MC) Sector 4 Lock Status

#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21)	// (MC) Sector 5 Lock Status

#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22)	// (MC) Sector 6 Lock Status

#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23)	// (MC) Sector 7 Lock Status

#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24)	// (MC) Sector 8 Lock Status

#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25)	// (MC) Sector 9 Lock Status

#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26)	// (MC) Sector 10 Lock Status

#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27)	// (MC) Sector 11 Lock Status

#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28)	// (MC) Sector 12 Lock Status

#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29)	// (MC) Sector 13 Lock Status

#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30)	// (MC) Sector 14 Lock Status

#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31)	// (MC) Sector 15 Lock Status

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface

// *****************************************************************************

typedef struct _AT91S_SPI

{

  AT91_REG SPI_CR;		// Control Register

  AT91_REG SPI_MR;		// Mode Register

  AT91_REG SPI_RDR;		// Receive Data Register

  AT91_REG SPI_TDR;		// Transmit Data Register

  AT91_REG SPI_SR;		// Status Register

  AT91_REG SPI_IER;		// Interrupt Enable Register

  AT91_REG SPI_IDR;		// Interrupt Disable Register

  AT91_REG SPI_IMR;		// Interrupt Mask Register

  AT91_REG Reserved0[4];	// 

  AT91_REG SPI_CSR[4];		// Chip Select Register

  AT91_REG Reserved1[48];	// 

  AT91_REG SPI_RPR;		// Receive Pointer Register

  AT91_REG SPI_RCR;		// Receive Counter Register

  AT91_REG SPI_TPR;		// Transmit Pointer Register

  AT91_REG SPI_TCR;		// Transmit Counter Register

  AT91_REG SPI_RNPR;		// Receive Next Pointer Register

  AT91_REG SPI_RNCR;		// Receive Next Counter Register

  AT91_REG SPI_TNPR;		// Transmit Next Pointer Register

  AT91_REG SPI_TNCR;		// Transmit Next Counter Register

  AT91_REG SPI_PTCR;		// PDC Transfer Control Register

  AT91_REG SPI_PTSR;		// PDC Transfer Status Register

} AT91S_SPI, *AT91PS_SPI;

// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 

#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0)	// (SPI) SPI Enable

#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1)	// (SPI) SPI Disable

#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7)	// (SPI) SPI Software reset

#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24)	// (SPI) SPI Last Transfer

// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 

#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0)	// (SPI) Master/Slave Mode

#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1)	// (SPI) Peripheral Select

#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1)	// (SPI) Fixed Peripheral Select

#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1)	// (SPI) Variable Peripheral Select

#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2)	// (SPI) Chip Select Decode

#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3)	// (SPI) Clock Selection

#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4)	// (SPI) Mode Fault Detection

#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7)	// (SPI) Clock Selection

#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16)	// (SPI) Peripheral Chip Select

#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24)	// (SPI) Delay Between Chip Selects

// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 

#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0)	// (SPI) Receive Data

#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16)	// (SPI) Peripheral Chip Select Status

// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 

#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0)	// (SPI) Transmit Data

#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16)	// (SPI) Peripheral Chip Select Status

// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 

#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0)	// (SPI) Receive Data Register Full

#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1)	// (SPI) Transmit Data Register Empty

#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2)	// (SPI) Mode Fault Error

#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3)	// (SPI) Overrun Error Status

#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4)	// (SPI) End of Receiver Transfer

#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5)	// (SPI) End of Receiver Transfer

#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6)	// (SPI) RXBUFF Interrupt

#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7)	// (SPI) TXBUFE Interrupt

#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8)	// (SPI) NSSR Interrupt

#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9)	// (SPI) TXEMPTY Interrupt

#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16)	// (SPI) Enable Status

// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 

// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 

// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 

// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 

#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0)	// (SPI) Clock Polarity

#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1)	// (SPI) Clock Phase

#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3)	// (SPI) Chip Select Active After Transfer

#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4)	// (SPI) Bits Per Transfer

#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4)	// (SPI) 8 Bits Per transfer

#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4)	// (SPI) 9 Bits Per transfer

#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4)	// (SPI) 10 Bits Per transfer

#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4)	// (SPI) 11 Bits Per transfer

#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4)	// (SPI) 12 Bits Per transfer

#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4)	// (SPI) 13 Bits Per transfer

#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4)	// (SPI) 14 Bits Per transfer

#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4)	// (SPI) 15 Bits Per transfer

#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4)	// (SPI) 16 Bits Per transfer

#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8)	// (SPI) Serial Clock Baud Rate

#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16)	// (SPI) Delay Before SPCK

#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24)	// (SPI) Delay Between Consecutive Transfers

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor

// *****************************************************************************

typedef struct _AT91S_ADC

{

  AT91_REG ADC_CR;		// ADC Control Register

  AT91_REG ADC_MR;		// ADC Mode Register

  AT91_REG Reserved0[2];	// 

  AT91_REG ADC_CHER;		// ADC Channel Enable Register

  AT91_REG ADC_CHDR;		// ADC Channel Disable Register

  AT91_REG ADC_CHSR;		// ADC Channel Status Register

  AT91_REG ADC_SR;		// ADC Status Register

  AT91_REG ADC_LCDR;		// ADC Last Converted Data Register

  AT91_REG ADC_IER;		// ADC Interrupt Enable Register

  AT91_REG ADC_IDR;		// ADC Interrupt Disable Register

  AT91_REG ADC_IMR;		// ADC Interrupt Mask Register

  AT91_REG ADC_CDR0;		// ADC Channel Data Register 0

  AT91_REG ADC_CDR1;		// ADC Channel Data Register 1

  AT91_REG ADC_CDR2;		// ADC Channel Data Register 2

  AT91_REG ADC_CDR3;		// ADC Channel Data Register 3

  AT91_REG ADC_CDR4;		// ADC Channel Data Register 4

  AT91_REG ADC_CDR5;		// ADC Channel Data Register 5

  AT91_REG ADC_CDR6;		// ADC Channel Data Register 6

  AT91_REG ADC_CDR7;		// ADC Channel Data Register 7

  AT91_REG Reserved1[44];	// 

  AT91_REG ADC_RPR;		// Receive Pointer Register

  AT91_REG ADC_RCR;		// Receive Counter Register

  AT91_REG ADC_TPR;		// Transmit Pointer Register

  AT91_REG ADC_TCR;		// Transmit Counter Register

  AT91_REG ADC_RNPR;		// Receive Next Pointer Register

  AT91_REG ADC_RNCR;		// Receive Next Counter Register

  AT91_REG ADC_TNPR;		// Transmit Next Pointer Register

  AT91_REG ADC_TNCR;		// Transmit Next Counter Register

  AT91_REG ADC_PTCR;		// PDC Transfer Control Register

  AT91_REG ADC_PTSR;		// PDC Transfer Status Register

} AT91S_ADC, *AT91PS_ADC;

// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 

#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0)	// (ADC) Software Reset

#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1)	// (ADC) Start Conversion

// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 

#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0)	// (ADC) Trigger Enable

#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0)	// (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software

#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1)	// (ADC) Hardware trigger selected by TRGSEL field is enabled.

#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1)	// (ADC) Trigger Selection

#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1)	// (ADC) Selected TRGSEL = TIAO0

#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1)	// (ADC) Selected TRGSEL = TIAO1

#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1)	// (ADC) Selected TRGSEL = TIAO2

#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1)	// (ADC) Selected TRGSEL = TIAO3

#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1)	// (ADC) Selected TRGSEL = TIAO4

#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1)	// (ADC) Selected TRGSEL = TIAO5

#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1)	// (ADC) Selected TRGSEL = External Trigger

#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4)	// (ADC) Resolution.

#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4)	// (ADC) 10-bit resolution

#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4)	// (ADC) 8-bit resolution

#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5)	// (ADC) Sleep Mode

#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5)	// (ADC) Normal Mode

#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5)	// (ADC) Sleep Mode

#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8)	// (ADC) Prescaler rate selection

#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16)	// (ADC) Startup Time

#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24)	// (ADC) Sample & Hold Time

// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 

#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0)	// (ADC) Channel 0

#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1)	// (ADC) Channel 1

#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2)	// (ADC) Channel 2

#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3)	// (ADC) Channel 3

#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4)	// (ADC) Channel 4

#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5)	// (ADC) Channel 5

#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6)	// (ADC) Channel 6

#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7)	// (ADC) Channel 7

// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 

// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 

// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 

#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0)	// (ADC) End of Conversion

#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1)	// (ADC) End of Conversion

#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2)	// (ADC) End of Conversion

#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3)	// (ADC) End of Conversion

#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4)	// (ADC) End of Conversion

#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5)	// (ADC) End of Conversion

#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6)	// (ADC) End of Conversion

#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7)	// (ADC) End of Conversion

#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8)	// (ADC) Overrun Error

#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9)	// (ADC) Overrun Error

#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10)	// (ADC) Overrun Error

#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11)	// (ADC) Overrun Error

#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12)	// (ADC) Overrun Error

#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13)	// (ADC) Overrun Error

#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14)	// (ADC) Overrun Error

#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15)	// (ADC) Overrun Error

#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16)	// (ADC) Data Ready

#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17)	// (ADC) General Overrun

#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18)	// (ADC) End of Receiver Transfer

#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19)	// (ADC) RXBUFF Interrupt

// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 

#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0)	// (ADC) Last Data Converted

// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 

// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 

// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 

// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 

#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0)	// (ADC) Converted Data

// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 

// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 

// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 

// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 

// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 

// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 

// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface

// *****************************************************************************

typedef struct _AT91S_SSC

{

  AT91_REG SSC_CR;		// Control Register

  AT91_REG SSC_CMR;		// Clock Mode Register

  AT91_REG Reserved0[2];	// 

  AT91_REG SSC_RCMR;		// Receive Clock ModeRegister

  AT91_REG SSC_RFMR;		// Receive Frame Mode Register

  AT91_REG SSC_TCMR;		// Transmit Clock Mode Register

  AT91_REG SSC_TFMR;		// Transmit Frame Mode Register

  AT91_REG SSC_RHR;		// Receive Holding Register

  AT91_REG SSC_THR;		// Transmit Holding Register

  AT91_REG Reserved1[2];	// 

  AT91_REG SSC_RSHR;		// Receive Sync Holding Register

  AT91_REG SSC_TSHR;		// Transmit Sync Holding Register

  AT91_REG SSC_RC0R;		// Receive Compare 0 Register

  AT91_REG SSC_RC1R;		// Receive Compare 1 Register

  AT91_REG SSC_SR;		// Status Register

  AT91_REG SSC_IER;		// Interrupt Enable Register

  AT91_REG SSC_IDR;		// Interrupt Disable Register

  AT91_REG SSC_IMR;		// Interrupt Mask Register

  AT91_REG Reserved3[44];	// 

  AT91_REG SSC_RPR;		// Receive Pointer Register

  AT91_REG SSC_RCR;		// Receive Counter Register

  AT91_REG SSC_TPR;		// Transmit Pointer Register

  AT91_REG SSC_TCR;		// Transmit Counter Register

  AT91_REG SSC_RNPR;		// Receive Next Pointer Register

  AT91_REG SSC_RNCR;		// Receive Next Counter Register

  AT91_REG SSC_TNPR;		// Transmit Next Pointer Register

  AT91_REG SSC_TNCR;		// Transmit Next Counter Register

  AT91_REG SSC_PTCR;		// PDC Transfer Control Register

  AT91_REG SSC_PTSR;		// PDC Transfer Status Register

} AT91S_SSC, *AT91PS_SSC;

// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 

#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0)	// (SSC) Receive Enable

#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1)	// (SSC) Receive Disable

#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8)	// (SSC) Transmit Enable

#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9)	// (SSC) Transmit Disable

#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15)	// (SSC) Software Reset

// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 

#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0)	// (SSC) Receive/Transmit Clock Selection

#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0)	// (SSC) Divided Clock

#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1)	// (SSC) TK Clock signal

#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2)	// (SSC) RK pin

#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2)	// (SSC) Receive/Transmit Clock Output Mode Selection

#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2)	// (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only

#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2)	// (SSC) Continuous Receive/Transmit Clock RK pin: Output

#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2)	// (SSC) Receive/Transmit Clock only during data transfers RK pin: Output

#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5)	// (SSC) Receive/Transmit Clock Inversion

#define AT91C_SSC_START       ((unsigned int) 0xF <<  8)	// (SSC) Receive/Transmit Start Selection

#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8)	// (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.

#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8)	// (SSC) Transmit/Receive start

#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8)	// (SSC) Detection of a low level on RF input

#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8)	// (SSC) Detection of a high level on RF input

#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8)	// (SSC) Detection of a falling edge on RF input

#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8)	// (SSC) Detection of a rising edge on RF input

#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8)	// (SSC) Detection of any level change on RF input

#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8)	// (SSC) Detection of any edge on RF input

#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8)	// (SSC) Compare 0

#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16)	// (SSC) Receive/Transmit Start Delay

#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24)	// (SSC) Receive/Transmit Period Divider Selection

// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 

#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0)	// (SSC) Data Length

#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5)	// (SSC) Loop Mode

#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7)	// (SSC) Most Significant Bit First

#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8)	// (SSC) Data Number per Frame

#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16)	// (SSC) Receive/Transmit Frame Sync length

#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20)	// (SSC) Receive/Transmit Frame Sync Output Selection

#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20)	// (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only

#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20)	// (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse

#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20)	// (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse

#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20)	// (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer

#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20)	// (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer

#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20)	// (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer

#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24)	// (SSC) Frame Sync Edge Detection

// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 

// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 

#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5)	// (SSC) Data Default Value

#define AT91C_SSC_MSBF	      ((unsigned int) 0x1 <<  7)	// (SSC) MSB First

#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23)	// (SSC) Frame Sync Data Enable

// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 

#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0)	// (SSC) Transmit Ready

#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1)	// (SSC) Transmit Empty

#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2)	// (SSC) End Of Transmission

#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3)	// (SSC) Transmit Buffer Empty

#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4)	// (SSC) Receive Ready

#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5)	// (SSC) Receive Overrun

#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6)	// (SSC) End of Reception

#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7)	// (SSC) Receive Buffer Full

#define AT91C_SSC_CP0         ((unsigned int) 0x1 <<  8)	// (SSC) Compare 0

#define AT91C_SSC_CP1         ((unsigned int) 0x1 <<  9)	// (SSC) Compare 1

#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10)	// (SSC) Transmit Sync

#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11)	// (SSC) Receive Sync

#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16)	// (SSC) Transmit Enable

#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17)	// (SSC) Receive Enable

// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 

// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 

// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Usart

// *****************************************************************************

typedef struct _AT91S_USART

{

  AT91_REG US_CR;		// Control Register

  AT91_REG US_MR;		// Mode Register

  AT91_REG US_IER;		// Interrupt Enable Register

  AT91_REG US_IDR;		// Interrupt Disable Register

  AT91_REG US_IMR;		// Interrupt Mask Register

  AT91_REG US_CSR;		// Channel Status Register

  AT91_REG US_RHR;		// Receiver Holding Register

  AT91_REG US_THR;		// Transmitter Holding Register

  AT91_REG US_BRGR;		// Baud Rate Generator Register

  AT91_REG US_RTOR;		// Receiver Time-out Register

  AT91_REG US_TTGR;		// Transmitter Time-guard Register

  AT91_REG Reserved0[5];	// 

  AT91_REG US_FIDI;		// FI_DI_Ratio Register

  AT91_REG US_NER;		// Nb Errors Register

  AT91_REG Reserved1[1];	// 

  AT91_REG US_IF;		// IRDA_FILTER Register

  AT91_REG Reserved2[44];	// 

  AT91_REG US_RPR;		// Receive Pointer Register

  AT91_REG US_RCR;		// Receive Counter Register

  AT91_REG US_TPR;		// Transmit Pointer Register

  AT91_REG US_TCR;		// Transmit Counter Register

  AT91_REG US_RNPR;		// Receive Next Pointer Register

  AT91_REG US_RNCR;		// Receive Next Counter Register

  AT91_REG US_TNPR;		// Transmit Next Pointer Register

  AT91_REG US_TNCR;		// Transmit Next Counter Register

  AT91_REG US_PTCR;		// PDC Transfer Control Register

  AT91_REG US_PTSR;		// PDC Transfer Status Register

} AT91S_USART, *AT91PS_USART;

// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 

#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9)	// (USART) Start Break

#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10)	// (USART) Stop Break

#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11)	// (USART) Start Time-out

#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12)	// (USART) Send Address

#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13)	// (USART) Reset Iterations

#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14)	// (USART) Reset Non Acknowledge

#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15)	// (USART) Rearm Time-out

#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16)	// (USART) Data Terminal ready Enable

#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17)	// (USART) Data Terminal ready Disable

#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18)	// (USART) Request to Send enable

#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19)	// (USART) Request to Send Disable

// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 

#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0)	// (USART) Usart mode

#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0)	// (USART) Normal

#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1)	// (USART) RS485

#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2)	// (USART) Hardware Handshaking

#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3)	// (USART) Modem

#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4)	// (USART) ISO7816 protocol: T = 0

#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6)	// (USART) ISO7816 protocol: T = 1

#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8)	// (USART) IrDA

#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC)	// (USART) Software Handshaking

#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4)	// (USART) Clock Selection (Baud Rate generator Input Clock

#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4)	// (USART) Clock

#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4)	// (USART) fdiv1

#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4)	// (USART) slow_clock (ARM)

#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4)	// (USART) External (SCK)

#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6)	// (USART) Clock Selection (Baud Rate generator Input Clock

#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6)	// (USART) Character Length: 5 bits

#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6)	// (USART) Character Length: 6 bits

#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6)	// (USART) Character Length: 7 bits

#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6)	// (USART) Character Length: 8 bits

#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8)	// (USART) Synchronous Mode Select

#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12)	// (USART) Number of Stop bits

#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12)	// (USART) 1 stop bit

#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12)	// (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits

#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12)	// (USART) 2 stop bits

#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16)	// (USART) Bit Order

#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17)	// (USART) 9-bit Character length

#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18)	// (USART) Clock Output Select

#define AT91C_US_OVER         ((unsigned int) 0x1 << 19)	// (USART) Over Sampling Mode

#define AT91C_US_INACK        ((unsigned int) 0x1 << 20)	// (USART) Inhibit Non Acknowledge

#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21)	// (USART) Disable Successive NACK

#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24)	// (USART) Number of Repetitions

#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28)	// (USART) Receive Line Filter

// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 

#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2)	// (USART) Break Received/End of Break

#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8)	// (USART) Receiver Time-out

#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10)	// (USART) Max number of Repetitions Reached

#define AT91C_US_NACK         ((unsigned int) 0x1 << 13)	// (USART) Non Acknowledge

#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16)	// (USART) Ring INdicator Input Change Flag

#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17)	// (USART) Data Set Ready Input Change Flag

#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18)	// (USART) Data Carrier Flag

#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19)	// (USART) Clear To Send Input Change Flag

// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 

// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 

// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 

#define AT91C_US_RI           ((unsigned int) 0x1 << 20)	// (USART) Image of RI Input

#define AT91C_US_DSR          ((unsigned int) 0x1 << 21)	// (USART) Image of DSR Input

#define AT91C_US_DCD          ((unsigned int) 0x1 << 22)	// (USART) Image of DCD Input

#define AT91C_US_CTS          ((unsigned int) 0x1 << 23)	// (USART) Image of CTS Input

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Two-wire Interface

// *****************************************************************************

typedef struct _AT91S_TWI

{

  AT91_REG TWI_CR;		// Control Register

  AT91_REG TWI_MMR;		// Master Mode Register

  AT91_REG Reserved0[1];	// 

  AT91_REG TWI_IADR;		// Internal Address Register

  AT91_REG TWI_CWGR;		// Clock Waveform Generator Register

  AT91_REG Reserved1[3];	// 

  AT91_REG TWI_SR;		// Status Register

  AT91_REG TWI_IER;		// Interrupt Enable Register

  AT91_REG TWI_IDR;		// Interrupt Disable Register

  AT91_REG TWI_IMR;		// Interrupt Mask Register

  AT91_REG TWI_RHR;		// Receive Holding Register

  AT91_REG TWI_THR;		// Transmit Holding Register

} AT91S_TWI, *AT91PS_TWI;

// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 

#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0)	// (TWI) Send a START Condition

#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1)	// (TWI) Send a STOP Condition

#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2)	// (TWI) TWI Master Transfer Enabled

#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3)	// (TWI) TWI Master Transfer Disabled

#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7)	// (TWI) Software Reset

// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 

#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8)	// (TWI) Internal Device Address Size

#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8)	// (TWI) No internal device address

#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8)	// (TWI) One-byte internal device address

#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8)	// (TWI) Two-byte internal device address

#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8)	// (TWI) Three-byte internal device address

#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12)	// (TWI) Master Read Direction

#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16)	// (TWI) Device Address

// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 

#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0)	// (TWI) Clock Low Divider

#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8)	// (TWI) Clock High Divider

#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16)	// (TWI) Clock Divider

// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 

#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0)	// (TWI) Transmission Completed

#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1)	// (TWI) Receive holding register ReaDY

#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2)	// (TWI) Transmit holding register ReaDY

#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6)	// (TWI) Overrun Error

#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7)	// (TWI) Underrun Error

#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8)	// (TWI) Not Acknowledged

// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 

// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 

// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface