Project

General

Profile

Download (9.56 KB) Statistics
| Branch: | Tag: | Revision:
1
/*
2
	FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
3

    
4
	This file is part of the FreeRTOS.org distribution.
5

    
6
	FreeRTOS.org is free software; you can redistribute it and/or modify
7
	it under the terms of the GNU General Public License as published by
8
	the Free Software Foundation; either version 2 of the License, or
9
	(at your option) any later version.
10

    
11
	FreeRTOS.org is distributed in the hope that it will be useful,
12
	but WITHOUT ANY WARRANTY; without even the implied warranty of
13
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
	GNU General Public License for more details.
15

    
16
	You should have received a copy of the GNU General Public License
17
	along with FreeRTOS.org; if not, write to the Free Software
18
	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19

    
20
	A special exception to the GPL can be applied should you wish to distribute
21
	a combined work that includes FreeRTOS.org, without being obliged to provide
22
	the source code for any proprietary components.  See the licensing section 
23
	of http://www.FreeRTOS.org for full details of how and when the exception
24
	can be applied.
25

    
26
	***************************************************************************
27
	See http://www.FreeRTOS.org for documentation, latest information, license 
28
	and contact details.  Please ensure to read the configuration and relevant 
29
	port sections of the online documentation.
30

    
31
	Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
32
	with commercial development and support options.
33
	***************************************************************************
34
*/
35

    
36
/*
37
	Changes from V3.2.3
38
	
39
	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
40

    
41
	Changes from V3.2.4
42

    
43
	+ Removed the use of the %0 parameter within the assembler macros and 
44
	  replaced them with hard coded registers.  This will ensure the
45
	  assembler does not select the link register as the temp register as
46
	  was occasionally happening previously.
47

    
48
	+ The assembler statements are now included in a single asm block rather
49
	  than each line having its own asm block.
50
*/
51

    
52
#ifndef PORTMACRO_H
53
#define PORTMACRO_H
54

    
55
/*-----------------------------------------------------------
56
 * Port specific definitions.  
57
 *
58
 * The settings in this file configure FreeRTOS correctly for the
59
 * given hardware and compiler.
60
 *
61
 * These settings should not be altered.
62
 *-----------------------------------------------------------
63
 */
64

    
65
/* Type definitions. */
66
#define portCHAR		char
67
#define portFLOAT		float
68
#define portDOUBLE		double
69
#define portLONG		long
70
#define portSHORT		short
71
#define portSTACK_TYPE	unsigned portLONG
72
#define portBASE_TYPE	portLONG
73

    
74
#if( configUSE_16_BIT_TICKS == 1 )
75
typedef unsigned portSHORT portTickType;
76
#define portMAX_DELAY ( portTickType ) 0xffff
77
#else
78
typedef unsigned portLONG portTickType;
79
#define portMAX_DELAY ( portTickType ) 0xffffffff
80
#endif
81
/*-----------------------------------------------------------*/
82

    
83
/* Architecture specifics. */
84
#define portSTACK_GROWTH			( -1 )
85
#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )
86
#define portBYTE_ALIGNMENT			4
87
#define portNOP()					asm volatile ( "NOP" );
88
/*-----------------------------------------------------------*/
89

    
90

    
91
/* Scheduler utilities. */
92

    
93
/*
94
 * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
95
 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
96
 * are included here for efficiency.  An attempt to call one from
97
 * THUMB mode code will result in a compile time error.
98
 */
99

    
100
#define portRESTORE_CONTEXT()											\
101
{																		\
102
extern volatile void * volatile pxCurrentTCB;							\
103
extern volatile unsigned portLONG ulCriticalNesting;					\
104
																		\
105
	/* Set the LR to the task stack. */									\
106
	asm volatile (														\
107
	"LDR		R0, =pxCurrentTCB								\n\t"	\
108
	"LDR		R0, [R0]										\n\t"	\
109
	"LDR		LR, [R0]										\n\t"	\
110
																		\
111
	/* The critical nesting depth is the first item on the stack. */	\
112
	/* Load it into the ulCriticalNesting variable. */					\
113
	"LDR		R0, =ulCriticalNesting							\n\t"	\
114
	"LDMFD	LR!, {R1}											\n\t"	\
115
	"STR		R1, [R0]										\n\t"	\
116
																		\
117
	/* Get the SPSR from the stack. */									\
118
	"LDMFD	LR!, {R0}											\n\t"	\
119
	"MSR		SPSR, R0										\n\t"	\
120
																		\
121
	/* Restore all system mode registers for the task. */				\
122
	"LDMFD	LR, {R0-R14}^										\n\t"	\
123
	"NOP														\n\t"	\
124
																		\
125
	/* Restore the return address. */									\
126
	"LDR		LR, [LR, #+60]									\n\t"	\
127
																		\
128
	/* And return - correcting the offset in the LR to obtain the */	\
129
	/* correct address. */												\
130
	"SUBS	PC, LR, #4											\n\t"	\
131
	);																	\
132
	( void ) ulCriticalNesting;											\
133
	( void ) pxCurrentTCB;												\
134
}
135
/*-----------------------------------------------------------*/
136

    
137
#define portSAVE_CONTEXT()												\
138
{																		\
139
extern volatile void * volatile pxCurrentTCB;							\
140
extern volatile unsigned portLONG ulCriticalNesting;					\
141
																		\
142
	/* Push R0 as we are going to use the register. */					\
143
	asm volatile (														\
144
	"STMDB	SP!, {R0}											\n\t"	\
145
																		\
146
	/* Set R0 to point to the task stack pointer. */					\
147
	"STMDB	SP,{SP}^											\n\t"	\
148
	"NOP														\n\t"	\
149
	"SUB	SP, SP, #4											\n\t"	\
150
	"LDMIA	SP!,{R0}											\n\t"	\
151
																		\
152
	/* Push the return address onto the stack. */						\
153
	"STMDB	R0!, {LR}											\n\t"	\
154
																		\
155
	/* Now we have saved LR we can use it instead of R0. */				\
156
	"MOV	LR, R0												\n\t"	\
157
																		\
158
	/* Pop R0 so we can save it onto the system mode stack. */			\
159
	"LDMIA	SP!, {R0}											\n\t"	\
160
																		\
161
	/* Push all the system mode registers onto the task stack. */		\
162
	"STMDB	LR,{R0-LR}^											\n\t"	\
163
	"NOP														\n\t"	\
164
	"SUB	LR, LR, #60											\n\t"	\
165
																		\
166
	/* Push the SPSR onto the task stack. */							\
167
	"MRS	R0, SPSR											\n\t"	\
168
	"STMDB	LR!, {R0}											\n\t"	\
169
																		\
170
	"LDR	R0, =ulCriticalNesting								\n\t"	\
171
	"LDR	R0, [R0]											\n\t"	\
172
	"STMDB	LR!, {R0}											\n\t"	\
173
																		\
174
	/* Store the new top of stack for the task. */						\
175
	"LDR	R0, =pxCurrentTCB									\n\t"	\
176
	"LDR	R0, [R0]											\n\t"	\
177
	"STR	LR, [R0]											\n\t"	\
178
	);																	\
179
	( void ) ulCriticalNesting;											\
180
	( void ) pxCurrentTCB;												\
181
}
182

    
183

    
184
/*-----------------------------------------------------------
185
 * ISR entry and exit macros.  These are only required if a task switch
186
 * is required from the ISR.
187
 *----------------------------------------------------------*/
188

    
189

    
190
#define portENTER_SWITCHING_ISR()										\
191
	/* Save the context of the interrupted task. */						\
192
	portSAVE_CONTEXT();													\
193
																		\
194
	/* We don't know the stack requirements for the ISR, so the frame */\
195
	/* pointer will be set to the top of the task stack, and the stack*/\
196
	/* pointer left where it is.  The IRQ stack will get used for any */\
197
	/* functions calls made by this ISR. */								\
198
	asm volatile ( "SUB		R11, LR, #4" );							\
199
	{
200

    
201
#define portEXIT_SWITCHING_ISR( SwitchRequired )						\
202
		/* If a switch is required then we just need to call */			\
203
		/* vTaskSwitchContext() as the context has already been */		\
204
		/* saved. */													\
205
		if( SwitchRequired )											\
206
		{																\
207
			vTaskSwitchContext();										\
208
		}																\
209
	}																	\
210
	/* Restore the context of which ever task is now the highest */		\
211
	/* priority that is ready to run. */								\
212
	portRESTORE_CONTEXT();
213

    
214
#define portYIELD()					asm volatile ( "SWI" );
215
/*-----------------------------------------------------------*/
216

    
217

    
218
/* Critical section management. */
219

    
220
/*
221
 * The interrupt management utilities can only be called from ARM mode.  When
222
 * THUMB_INTERWORK is defined the utilities are defined as functions in 
223
 * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not 
224
 * defined then the utilities are defined as macros here - as per other ports.
225
 */
226

    
227
#ifdef THUMB_INTERWORK
228

    
229
extern void vPortDisableInterruptsFromThumb (void) __attribute__ ((naked));
230
extern void vPortEnableInterruptsFromThumb (void) __attribute__ ((naked));
231

    
232
#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
233
#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
234

    
235
#else
236

    
237
#define portDISABLE_INTERRUPTS()											\
238
		asm volatile (															\
239
			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
240
			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
241
			"ORR	R0, R0, #0x80	\n\t"	/* Disable IRQ, don't diable FIQ.			*/	\
242
			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
243
			"LDMIA	SP!, {R0}			" )	/* Pop R0.                                              */
244

    
245
#define portENABLE_INTERRUPTS()												\
246
		asm volatile (															\
247
			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
248
			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
249
			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
250
			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
251
			"LDMIA	SP!, {R0}			" )	/* Pop R0.                                              */
252

    
253
#endif /* THUMB_INTERWORK */
254

    
255
extern void vPortEnterCritical (void);
256
extern void vPortExitCritical (void);
257

    
258
#define portENTER_CRITICAL()		vPortEnterCritical();
259
#define portEXIT_CRITICAL()			vPortExitCritical();
260
/*-----------------------------------------------------------*/
261

    
262
/* Task function macros as described on the FreeRTOS.org WEB site. */
263
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
264
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
265

    
266
#endif /* PORTMACRO_H */
(6-6/6)
Add picture from clipboard (Maximum size: 48.8 MB)