Cisco AS5400 » History » Version 8
laforge, 09/24/2023 06:28 PM
| 1 | 3 | laforge | {{>toc}} |
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| 3 | 1 | laforge | h1. Cisco AS5400 |
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| 5 | This is a modular access server for voice, data (ISDN) and modem calls. It has a modular archticture and there are a variety of suitable modules. |
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| 7 | 8 | laforge | The System consists of PSU, a Mainboard, a backplane and three trays. Each of the three Trays can house two modules. The mainboard also directly houses one module. |
| 8 | 4 | laforge | |
| 9 | 1 | laforge | * attachment:Cisco_AS5350_AS5400_Software_Configuration_Guide.pdf |
| 10 | 6 | laforge | |
| 11 | h2. Mainboard |
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| 12 | |||
| 13 | * 2x Gigabit Ethernet: Broadcom BCM5481 |
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| 14 | * 1x coaxial BITS (timing): Dallas DS2 |
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| 15 | * 1x Marvell GT-96124-B-2 F55551.0 |
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| 16 | * Altera Cyclone EP1C4F400C8 |
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| 17 | * Xilinx Spartan XC2S300E |
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| 18 | * PI7C8150 PCI bridge (module to backplane) |
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| 19 | * PI7C8150 PCI bridge (CPU to backplane) |
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| 20 | * PI7C8150 PCI bridge (unused PCI slot) |
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| 21 | * 1x unknown under natural color heatsink |
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| 22 | * 1x unknown under black anodized heatsink (700-09863-01 REV A0 / VETTE 0824) |
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| 23 | * CompactFlash slot with 128MB CF card |
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| 24 | * Memory slot holding STEC STM122116RT 512MB 2R8 PC2700E CL2.5-3-3 RAM |
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| 26 | 1 | laforge | |
| 27 | 4 | laforge | h2. Trays |
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| 29 | 5 | laforge | The tray has one connection to the backplane, and two proprietary high-density connectors for the two modules. |
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| 31 | The central TDM component on the Tray is the Zarlink *MT90866* _2432x2432 non-blocking digital switch with H.110 interface_ (data sheet see attachment:MT90866.pdf. |
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| 33 | Each module's PCI bus is bridged to the backplane PCI using a Pericum *PI7C8150* _2-port PCI-to-PCI Bridge_ (data sheet see attachment:PI7C8150.pdf) |
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| 34 | 4 | laforge | |
| 35 | 1 | laforge | h2. Modem modules |
| 36 | 3 | laforge | |
| 37 | h3. NP108 module |
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| 38 | 1 | laforge | |
| 39 | 4 | laforge | This module is built around 18x Conexant/Mindspeed *RL56CSMV/6* chips (data sheet see attachment:RL56CSMV_6.pdf). Each of the chips features its own *MT48LC4M16A2* RAM chip. Internally, each of those chips contains an _ARM core_ for management, and six _Digital Data Pump_ dies. |
| 40 | 2 | laforge | |
| 41 | 1 | laforge | Interfacing with the backplane is done via 3x Intel i960. |
| 42 | 2 | laforge | |
| 43 | 3 | laforge | |
| 44 | 1 | laforge | h3. NP60 module |
| 45 | 2 | laforge | |
| 46 | 4 | laforge | This module is the little brother of the NP108. It is built around 10x Conexant/Mindspeed *RL56CSMV/6* chips (data sheet see attachment:RL56CSMV_6.pdf). Each of the chips features its own *MT48LC4M16A2* RAM chip. Internally, each of those chips contains an _ARM core_ for management, and six _Digital Data Pump_ dies. |
| 47 | 1 | laforge | |
| 48 | 3 | laforge | Interfacing with the backplane is done via 2x Intel i960. |
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| 50 | 7 | laforge | h3. Power Supply |
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| 52 | {{thumbnail(20220422_162511.jpg)}} |
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| 53 | {{thumbnail(20220422_162507.jpg)}} |
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| 54 | {{thumbnail(20220422_162503.jpg)}} |
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| 55 | {{thumbnail(20220422_162503.jpg)}} |
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| 56 | {{thumbnail(20220422_162501.jpg)}} |
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| 58 | 3 | laforge | h2. Trunk interface modules |
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| 60 | h3. 8PRI |
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| 61 | 1 | laforge | |
| 62 | This is an 8x PRI (E1/T1) interface. |
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| 63 | 3 | laforge | |
| 64 | 4 | laforge | Each PRI interface has its own EMI / overvoltage / transforer section, followed by a Mindspeed *Bt8370KPF* E1/Ta transceiver (datasheet see attachment:Bt8370KPF.pdf). The main CPU is an MPC860 PowerPC, interfaced via a PLX *PCI9054* PCI bridge (datasheet see attachment:PCI9054.pdf). |
| 65 | 3 | laforge | |
| 66 | 4 | laforge | There are also two PMC FREEDM8 *PM7366* _Eight Channel Frame Engine and Datalink Manager_ (datasheet see attachment:PM7366.pdf). |
