Cisco AS5400 » History » Version 4
laforge, 03/05/2022 08:21 PM
| 1 | 3 | laforge | {{>toc}} |
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| 3 | 1 | laforge | h1. Cisco AS5400 |
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| 5 | This is a modular access server for voice, data (ISDN) and modem calls. It has a modular archticture and there are a variety of suitable modules. |
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| 7 | 4 | laforge | The System consists of a Mainboard, a backplane and three trays. Each of the three Trays can house two modules. |
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| 9 | 1 | laforge | * attachment:Cisco_AS5350_AS5400_Software_Configuration_Guide.pdf |
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| 11 | 4 | laforge | h2. Trays |
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| 13 | The tray has one connection to the backplane, and two proprietary high-density connectors for the two modules. The central component on the Tray is the Zarlink *MT90866* _2432x2432 non-blocking digital switch with H.110 interface_ (data sheet see attachment:MT90866.pdf |
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| 15 | 1 | laforge | h2. Modem modules |
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| 17 | h3. NP108 module |
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| 18 | 1 | laforge | |
| 19 | 4 | laforge | This module is built around 18x Conexant/Mindspeed *RL56CSMV/6* chips (data sheet see attachment:RL56CSMV_6.pdf). Each of the chips features its own *MT48LC4M16A2* RAM chip. Internally, each of those chips contains an _ARM core_ for management, and six _Digital Data Pump_ dies. |
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| 21 | 1 | laforge | Interfacing with the backplane is done via 3x Intel i960. |
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| 23 | 3 | laforge | |
| 24 | 1 | laforge | h3. NP60 module |
| 25 | 2 | laforge | |
| 26 | 4 | laforge | This module is the little brother of the NP108. It is built around 10x Conexant/Mindspeed *RL56CSMV/6* chips (data sheet see attachment:RL56CSMV_6.pdf). Each of the chips features its own *MT48LC4M16A2* RAM chip. Internally, each of those chips contains an _ARM core_ for management, and six _Digital Data Pump_ dies. |
| 27 | 1 | laforge | |
| 28 | 3 | laforge | Interfacing with the backplane is done via 2x Intel i960. |
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| 30 | h2. Trunk interface modules |
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| 32 | h3. 8PRI |
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| 34 | This is an 8x PRI (E1/T1) interface. |
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| 36 | 4 | laforge | Each PRI interface has its own EMI / overvoltage / transforer section, followed by a Mindspeed *Bt8370KPF* E1/Ta transceiver (datasheet see attachment:Bt8370KPF.pdf). The main CPU is an MPC860 PowerPC, interfaced via a PLX *PCI9054* PCI bridge (datasheet see attachment:PCI9054.pdf). |
| 37 | 3 | laforge | |
| 38 | 4 | laforge | There are also two PMC FREEDM8 *PM7366* _Eight Channel Frame Engine and Datalink Manager_ (datasheet see attachment:PM7366.pdf). |
