Architecture » History » Version 6
laforge, 02/21/2016 08:51 AM
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2 | 5 | h1. [[UmTRX]] architecture |
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5 | 4 | The LMS6002D FPRF ICs provide analogue filtering, VGAs, VCOs and mixers etc. in addition to performing digital conversion. |
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7 | 1 | DC offset and IQ balance correction is implemented in the front-end in the FPGA. |
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9 | 5 | Host connection is via gigabit Ethernet and samples along with timestamps and system settings such as frequency, gain and bandwidth, are encapsulated in "VITA Radio Transport":http://www.vita.com/home/Specification/Specifications.html (VRT) packets. |
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11 | 4 | Higher TX and RX sample rates are used in the front-end than in communication with the host, and half-band and CIC filters implemented in the FPGA are used to perform up/down-conversion, with amplitude correction in place pre (RX) and post (TX) filtering. This allows the frequency to be shifted within the original sample rate and without having to re-tune the LMS6002D transceiver. |
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13 | After filtering, RX samples are immediately forwarded to the host by Ethernet packet router. |
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15 | TX packets received from the host are buffered by a SRAM FIFO to help ensure that there are always samples to transmit. |
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17 | 1 | RX samples are time-stamped and TX samples can be sent at a precise time, ensuring that TX and RX are perfectly aligned (this is critical for TDM systems). |
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20 | 5 | h2. High level |
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23 | 6 | laforge | !{width=100%}UmTRX.png! |
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26 | h2. FPGA |
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29 | 6 | laforge | !{width=100%}FPGA_structure.png! |