simtrace/hardware/kicad/simadapter1.sch @ master
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EESchema Schematic File Version 2 date Sat 18 Feb 2012 04:48:32 PM CET |
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LIBS:power |
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LIBS:device |
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LIBS:transistors |
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LIBS:conn |
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LIBS:linear |
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LIBS:regul |
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LIBS:74xx |
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LIBS:cmos4000 |
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LIBS:adc-dac |
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LIBS:memory |
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LIBS:xilinx |
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LIBS:special |
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LIBS:microcontrollers |
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LIBS:dsp |
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LIBS:microchip |
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LIBS:analog_switches |
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LIBS:motorola |
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LIBS:texas |
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LIBS:intel |
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LIBS:audio |
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LIBS:interface |
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LIBS:digital-audio |
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LIBS:philips |
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LIBS:display |
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LIBS:cypress |
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LIBS:siliconi |
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LIBS:opto |
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LIBS:atmel |
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LIBS:contrib |
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LIBS:valves |
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LIBS:smartcard |
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EELAYER 43 0 |
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EELAYER END |
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$Descr A4 11700 8267 |
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encoding utf-8 |
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Sheet 1 1 |
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Title "" |
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Date "18 feb 2012" |
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Rev "" |
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Comp "" |
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Comment1 "" |
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Comment2 "" |
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Comment3 "" |
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Comment4 "" |
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$EndDescr |
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Wire Wire Line |
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5750 2450 6100 2450 |
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Wire Wire Line |
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6100 2450 6100 1900 |
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Wire Wire Line |
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6100 1900 5200 1900 |
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Wire Wire Line |
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5200 1900 5200 1650 |
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Wire Wire Line |
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5750 2250 5900 2250 |
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Wire Wire Line |
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5900 2250 5900 1700 |
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Wire Wire Line |
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5900 1700 5400 1700 |
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Wire Wire Line |
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5400 1700 5400 1650 |
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Wire Wire Line |
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4650 2350 4400 2350 |
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Wire Wire Line |
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4400 2350 4400 1800 |
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Wire Wire Line |
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4400 1800 5000 1800 |
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Wire Wire Line |
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5000 1800 5000 1650 |
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Wire Wire Line |
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4650 2250 4500 2250 |
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Wire Wire Line |
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4500 2250 4500 1700 |
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Wire Wire Line |
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4500 1700 4900 1700 |
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Wire Wire Line |
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4900 1700 4900 1650 |
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Wire Wire Line |
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5100 1650 5100 1900 |
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Wire Wire Line |
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5100 1900 4300 1900 |
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Wire Wire Line |
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4300 1900 4300 2450 |
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Wire Wire Line |
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4300 2450 4650 2450 |
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Wire Wire Line |
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5300 1650 5300 1800 |
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Wire Wire Line |
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5300 1800 6000 1800 |
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Wire Wire Line |
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6000 1800 6000 2350 |
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Wire Wire Line |
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6000 2350 5750 2350 |
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$Comp |
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L ISO7816_NO P2 |
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U 1 1 4F3FBFC0 |
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P 5200 2400 |
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F 0 "P2" H 5200 2650 60 0000 C CNN |
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F 1 "ISO7816_NO" H 5200 2150 60 0000 C CNN |
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1 5200 2400 |
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1 0 0 -1 |
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$EndComp |
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$Comp |
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L REBELSIM P1 |
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U 1 1 4F3FBFB5 |
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P 5150 1300 |
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F 0 "P1" H 5200 1650 60 0000 C CNN |
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F 1 "REBELSIM" V 5350 1300 60 0000 C CNN |
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1 5150 1300 |
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0 -1 -1 0 |
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$EndComp |
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$EndSCHEMATC |
