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/* OpenPICC TC (Timer / Clock) support code
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* (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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/* PICC Simulator Side:
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* In order to support responding to synchronous frames (REQA/WUPA/ANTICOL),
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* we need a second Timer/Counter (TC2). This unit is reset by an external
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* event (rising edge of modulation pause PCD->PICC, falling edge of
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* demodulated data) connected to TIOB2, and counts up to a configurable
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* number of carrier clock cycles (RA). Once the RA value is reached, TIOA2
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* will see a rising edge. This rising edge will be interconnected to TF (Tx
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* Frame) of the SSC to start transmitting our synchronous response.
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*
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*/
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#include <lib_AT91SAM7.h>
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#include <AT91SAM7.h>
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#include <os/dbgu.h>
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#include "../openpcd.h"
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#include <os/tc_cdiv.h>
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#include <picc/tc_fdt.h>
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static AT91PS_TC tcfdt = AT91C_BASE_TC2;
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void tc_fdt_set(uint16_t count)
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{
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tcfdt->TC_RA = count;
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}
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/* 'count' number of carrier cycles after the last modulation pause,
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* we deem the frame to have ended */
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void tc_frame_end_set(uint16_t count)
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{
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tcfdt->TC_RB = count;
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}
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static void tc_fdt_irq(void)
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{
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uint32_t sr = tcfdt->TC_SR;
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DEBUGP("tc_fdt_irq: TC2_SR=0x%08x TC2_CV=0x%08x ",
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sr, tcfdt->TC_CV);
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if (sr & AT91C_TC_ETRGS) {
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DEBUGP("Ext_trigger ");
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}
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if (sr & AT91C_TC_CPAS) {
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DEBUGP("FDT_expired ");
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/* FIXME: if we are in anticol / sync mode,
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* we could do software triggering of SSC TX,
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* but IIRC the hardware does this by TF */
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}
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if (sr & AT91C_TC_CPBS) {
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DEBUGP("Frame_end ");
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/* FIXME: stop ssc (in continuous mode),
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* take care of preparing synchronous response if
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* we operate in anticol mode.*/
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}
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if (sr & AT91C_TC_CPCS) {
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DEBUGP("Compare_C ");
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}
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DEBUGPCR("");
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}
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void tc_fdt_print(void)
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{
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DEBUGP("TC2_CV=0x%08x ", tcfdt->TC_CV);
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DEBUGP("TC2_CMR=0x%08x ", tcfdt->TC_CMR);
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DEBUGP("TC2_SR=0x%08x ", tcfdt->TC_SR);
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DEBUGP("TC2_RA=0x%04x, TC2_RB=0x%04x, TC2_RC=0x%04x",
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tcfdt->TC_RA, tcfdt->TC_RB, tcfdt->TC_RC);
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}
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void tc_fdt_init(void)
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{
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AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA15_TF,
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AT91C_PA26_TIOA2 | AT91C_PA27_TIOB2);
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AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
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((unsigned int) 1 << AT91C_ID_TC2));
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/* Enable Clock for TC2 */
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tcfdt->TC_CCR = AT91C_TC_CLKEN;
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tcfdt->TC_RC = 0xffff;
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tc_frame_end_set(128*2);
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/* Clock XC1, Wave Mode, No automatic reset on RC comp
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* TIOA2 in RA comp = set, TIOA2 on RC comp = clear,
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* TIOA2 on EEVT = clear
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* TIOB2 as input, EEVT = TIOB2, Reset/Trigger on EEVT */
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tcfdt->TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
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AT91C_TC_WAVESEL_UP |
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AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR |
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AT91C_TC_AEEVT_CLEAR |
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AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE |
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AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_FALLING |
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AT91C_TC_ENETRG | AT91C_TC_CPCSTOP ;
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/* Reset to start timers */
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tcb->TCB_BCR = 1;
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AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_TC2,
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OPENPCD_IRQ_PRIO_TC_FDT,
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AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &tc_fdt_irq);
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AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_TC2);
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tcfdt->TC_IER = AT91C_TC_CPAS | AT91C_TC_CPBS | AT91C_TC_CPCS |
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AT91C_TC_ETRGS;
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}
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