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/* AT91SAM7 SSC controller routines for OpenPICC
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* (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* We use SSC for both TX and RX side.
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*
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* RX side is interconnected with demodulated carrier
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*
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* TX side is interconnected with load modulation circuitry
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*/
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//#undef DEBUG
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#include <errno.h>
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#include <string.h>
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#include <sys/types.h>
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#include <AT91SAM7.h>
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#include <lib_AT91SAM7.h>
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#include <openpcd.h>
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33
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#include <os/usb_handler.h>
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#include <os/dbgu.h>
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#include <os/led.h>
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#include "../openpcd.h"
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38
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#include <picc/tc_cdiv_sync.h>
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40
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//#define DEBUG_SSC_REFILL
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42
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43
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/* definitions for four-times oversampling */
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44
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#define REQA 0x10410441
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45
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#define WUPA 0x04041041
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46
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static const AT91PS_SSC ssc = AT91C_BASE_SSC;
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48
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static AT91PS_PDC rx_pdc;
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49
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enum ssc_mode {
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SSC_MODE_NONE,
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52
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SSC_MODE_14443A_SHORT,
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53
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SSC_MODE_14443A_STANDARD,
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54
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SSC_MODE_14443B,
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SSC_MODE_EDGE_ONE_SHOT,
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SSC_MODE_CONTINUOUS,
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57
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};
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58
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struct ssc_state {
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struct req_ctx *rx_ctx[2];
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enum ssc_mode mode;
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};
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static struct ssc_state ssc_state;
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64
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static const uint16_t ssc_dmasize[] = {
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[SSC_MODE_NONE] = 16,
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[SSC_MODE_14443A_SHORT] = 16, /* 64 bytes */
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68
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[SSC_MODE_14443A_STANDARD] = 16, /* 64 bytes */
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[SSC_MODE_14443B] = 16, /* 64 bytes */
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[SSC_MODE_EDGE_ONE_SHOT] = 16, /* 64 bytes */
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[SSC_MODE_CONTINUOUS] = 511, /* 2044 bytes */
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};
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/* This is for four-times oversampling */
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#define ISO14443A_SOF_SAMPLE 0x01
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#define ISO14443A_SOF_LEN 4
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#define SSC_RX_IRQ_MASK (AT91C_SSC_RXRDY | \
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AT91C_SSC_OVRUN | \
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AT91C_SSC_ENDRX | \
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AT91C_SSC_RXBUFF | \
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AT91C_SSC_RXSYN | \
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AT91C_SSC_CP0 | \
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AT91C_SSC_CP1)
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85
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#define SSC_TX_IRQ_MASK (AT91C_SSC_TXRDY | \
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AT91C_SSC_TXEMPTY | \
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AT91C_SSC_ENDTX | \
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AT91C_SSC_TXBUFE | \
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AT91C_SSC_TXSYN)
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91
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void ssc_rx_mode_set(enum ssc_mode ssc_mode)
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{
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uint8_t data_len, num_data, sync_len;
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uint32_t start_cond;
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96
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/* disable Rx and all Rx interrupt sources */
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AT91F_SSC_DisableRx(AT91C_BASE_SSC);
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AT91F_SSC_DisableIt(ssc, SSC_RX_IRQ_MASK);
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switch (ssc_mode) {
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case SSC_MODE_14443A_SHORT:
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start_cond = AT91C_SSC_START_0;
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sync_len = ISO14443A_SOF_LEN;
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ssc->SSC_RC0R = ISO14443A_SOF_SAMPLE;
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data_len = 32;
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num_data = 16;
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break;
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case SSC_MODE_14443A_STANDARD:
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start_cond = AT91C_SSC_START_0;
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sync_len = ISO14443A_SOF_LEN;
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ssc->SSC_RC0R = ISO14443A_SOF_SAMPLE;
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data_len = 32;
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num_data = 16; /* FIXME */
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break;
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case SSC_MODE_14443B:
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/* start sampling at first falling data edge */
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//start_cond =
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break;
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case SSC_MODE_EDGE_ONE_SHOT:
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case SSC_MODE_CONTINUOUS:
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/* unfortunately we don't have RD and RF interconnected
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* (at least not yet in the current hardware) */
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//start_cond = AT91C_SSC_START_EDGE_RF;
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start_cond = AT91C_SSC_START_CONTINOUS;
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//AT91C_SSC_START_RISE_RF;
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sync_len = 0;
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data_len = 32;
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num_data = 16;
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break;
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case SSC_MODE_NONE:
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goto out_set_mode;
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break;
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}
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//ssc->SSC_RFMR = AT91C_SSC_MSBF | (data_len-1) & 0x1f |
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ssc->SSC_RFMR = (data_len-1) & 0x1f |
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(((num_data-1) & 0x0f) << 8) |
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(((sync_len-1) & 0x0f) << 16);
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ssc->SSC_RCMR = AT91C_SSC_CKS_RK | AT91C_SSC_CKO_NONE |
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(0x2 << 6) | AT91C_SSC_CKI | start_cond;
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/* Enable Rx DMA */
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AT91F_PDC_EnableRx(rx_pdc);
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/* Enable RX interrupts */
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AT91F_SSC_EnableIt(ssc, AT91C_SSC_OVRUN | AT91C_SSC_CP0 |
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AT91C_SSC_ENDRX | AT91C_SSC_RXBUFF);
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out_set_mode:
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ssc_state.mode = ssc_mode;
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}
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static void ssc_tx_mode_set(enum ssc_mode ssc_mode)
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{
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uint8_t data_len, num_data, sync_len;
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uint32_t start_cond;
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156
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/* disable Tx */
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AT91F_SSC_DisableTx(AT91C_BASE_SSC);
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159
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/* disable all Tx related interrupt sources */
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AT91F_SSC_DisableIt(ssc, SSC_TX_IRQ_MASK);
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switch (ssc_mode) {
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case SSC_MODE_14443A_SHORT:
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start_cond = AT91C_SSC_START_RISE_RF;
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sync_len = 0;
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data_len = 32;
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num_data = 1;
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break;
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case SSC_MODE_14443A_STANDARD:
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start_cond = AT91C_SSC_START_0;
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sync_len = ISO14443A_SOF_LEN;
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ssc->SSC_RC0R = ISO14443A_SOF_SAMPLE;
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data_len = 32;
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num_data = 1; /* FIXME */
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break;
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}
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ssc->SSC_TFMR = (data_len-1) & 0x1f |
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(((num_data-1) & 0x0f) << 8) |
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(((sync_len-1) & 0x0f) << 16);
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ssc->SSC_TCMR = AT91C_SSC_CKS_RK | AT91C_SSC_CKO_NONE | start_cond;
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AT91F_SSC_EnableIt(ssc, AT91C_SSC_TXSYN);
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AT91F_SSC_EnableTx(AT91C_BASE_SSC);
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#if 0
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/* Enable RX interrupts */
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AT91F_SSC_EnableIt(ssc, AT91C_SSC_OVRUN |
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AT91C_SSC_ENDTX | AT91C_SSC_TXBUFE);
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AT91F_PDC_EnableTx(tx_pdc);
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ssc_state.mode = ssc_mode;
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#endif
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}
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196
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197
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static struct openpcd_hdr opcd_ssc_hdr = {
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.cmd = OPENPCD_CMD_SSC_READ,
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};
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static inline void init_opcdhdr(struct req_ctx *rctx)
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{
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memcpy(rctx->data, &opcd_ssc_hdr, sizeof(opcd_ssc_hdr));
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rctx->tot_len = sizeof(opcd_ssc_hdr);
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}
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#define DEBUG_SSC_REFILL 1
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#ifdef DEBUG_SSC_REFILL
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#define DEBUGR(x, args ...) DEBUGPCRF(x, ## args)
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#else
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#define DEBUGR(x, args ...)
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#endif
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214
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static int __ramfunc __ssc_rx_refill(int secondary)
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{
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struct req_ctx *rctx;
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rctx = req_ctx_find_get(1, RCTX_STATE_FREE, RCTX_STATE_SSC_RX_BUSY);
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if (!rctx) {
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DEBUGP("no_rctx_for_refill! ");
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return -1;
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}
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init_opcdhdr(rctx);
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DEBUGR("filling SSC RX%u dma ctx: %u (len=%u) ", secondary,
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req_ctx_num(rctx), rctx->size);
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rctx->tot_len = ssc_dmasize[ssc_state.mode]*4 +
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sizeof(struct openpcd_hdr);
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if (secondary) {
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AT91F_PDC_SetNextRx(rx_pdc, rctx->data+MAX_HDRSIZE,
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ssc_dmasize[ssc_state.mode]);
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ssc_state.rx_ctx[1] = rctx;
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233
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} else {
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234
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AT91F_PDC_SetRx(rx_pdc, rctx->data+MAX_HDRSIZE,
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235
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ssc_dmasize[ssc_state.mode]);
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ssc_state.rx_ctx[0] = rctx;
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}
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238
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239
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tc_cdiv_sync_reset();
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240
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241
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return 0;
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242
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}
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243
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244
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#if 0
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245
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static char dmabuf1[512];
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246
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static char dmabuf2[512];
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247
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248
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/* Try to refill RX dma descriptors. Return values:
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* 0) no dma descriptors empty
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250
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* 1) filled next/secondary descriptor
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251
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* 2) filled both primary and secondary descriptor
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252
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* -1) no free request contexts to use
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253
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* -2) only one free request context, but two free descriptors
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254
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*/
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255
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static int8_t ssc_rx_refill(void)
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256
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{
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257
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struct req_ctx *rctx;
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258
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DEBUGR("refill ");
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259
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#if 1
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260
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rctx = req_ctx_find_get(1, RCTX_STATE_FREE, RCTX_STATE_SSC_RX_BUSY);
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261
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DEBUGP("SSC_SR=0x%08x ", ssc->SSC_SR);
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262
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if (AT91F_PDC_IsRxEmpty(rx_pdc)) {
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263
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DEBUGR("filling primary SSC RX dma ctx: %u (len=%u) ",
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264
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req_ctx_num(rctx), rctx->size);
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265
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rctx->tot_len = rctx->size;
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266
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AT91F_PDC_SetRx(rx_pdc, rctx->data+MAX_HDRSIZE,
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267
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(rctx->size-MAX_HDRSIZE)>>2);
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268
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ssc_state.rx_ctx[0] = rctx;
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269
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270
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/* If primary is empty, secondary must be empty, too */
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271
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rctx = req_ctx_find_get(1, RCTX_STATE_FREE,
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272
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RCTX_STATE_SSC_RX_BUSY);
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273
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if (!rctx) {
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274
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DEBUGPCRF("no rctx for secondary refill!");
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275
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return -2;
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276
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}
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277
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init_opcdhdr(rctx);
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278
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}
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279
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|
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280
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if (AT91F_PDC_IsNextRxEmpty(rx_pdc)) {
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281
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DEBUGR("filling secondary SSC RX dma ctx: %u (len=%u) ",
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282
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req_ctx_num(rctx), rctx->size);
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283
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rctx->tot_len = rctx->size;
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284
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AT91F_PDC_SetNextRx(rx_pdc, rctx->data+MAX_HDRSIZE,
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285
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(rctx->size-MAX_HDRSIZE)>2);
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286
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ssc_state.rx_ctx[1] = rctx;
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287
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return 2;
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|
288
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} else {
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289
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/* we were unable to fill*/
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|
290
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DEBUGPCRF("prim/secnd DMA busy, can't refill");
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291
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req_ctx_put(rctx);
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292
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return 0;
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|
293
|
}
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|
294
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#else
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|
295
|
if (AT91F_PDC_IsRxEmpty(rx_pdc))
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296
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AT91F_PDC_SetRx(rx_pdc, dmabuf1, sizeof(dmabuf1)>>2);
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297
|
|
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298
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if (AT91F_PDC_IsNextRxEmpty(rx_pdc))
|
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299
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AT91F_PDC_SetNextRx(rx_pdc, dmabuf2, sizeof(dmabuf2)>>2);
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300
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else
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|
301
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DEBUGPCRF("prim/secnd DMA busy, can't refill");
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302
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#endif
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|
303
|
}
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|
304
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#endif
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|
305
|
|
|
306
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#define ISO14443A_FDT_SHORT_1 1236
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307
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#define ISO14443A_FDT_SHORT_0 1172
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|
308
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|
|
309
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static void __ramfunc ssc_irq(void)
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|
310
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{
|
|
311
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uint32_t ssc_sr = ssc->SSC_SR;
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312
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int i, *tmp, emptyframe = 0;
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313
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DEBUGP("ssc_sr=0x%08x, mode=%u: ", ssc_sr, ssc_state.mode);
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|
314
|
|
|
315
|
if (ssc_sr & AT91C_SSC_ENDRX) {
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|
316
|
#if 1
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|
317
|
/* in a one-shot sample, we don't want to keep
|
|
318
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* sampling further after having received the first
|
|
319
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* packet. */
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|
320
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if (ssc_state.mode == SSC_MODE_EDGE_ONE_SHOT) {
|
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321
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DEBUGP("DISABLE_RX ");
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|
322
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ssc_rx_stop();
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|
323
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}
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|
324
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//AT91F_SSC_DisableIt(AT91C_BASE_SSC, SSC_RX_IRQ_MASK);
|
|
325
|
#endif
|
|
326
|
#if 0
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|
327
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/* Experimental start SSC on frame, stop on FFFFFFFF */
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|
328
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if (ssc_state.mode == SSC_MODE_CONTINUOUS) {
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329
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//ssc->SSC_RCMR = (ssc->SSC_RCMR & ~AT91C_SSC_START) | AT91C_SSC_START_CONTINOUS;
|
|
330
|
tmp = (uint32_t*)ssc_state.rx_ctx[0]->data;
|
|
331
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for(i = ssc_state.rx_ctx[0]->size / 4; i >= 0 ; i--) {
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|
332
|
if( *tmp++ == 0xFFFFFFFF ) {
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|
333
|
*(tmp-1) = 0xAAAAAAAA; // debug marker
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|
334
|
/* No modulation for a long time, stop sampling
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|
335
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* and prepare for next frame */
|
|
336
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DEBUGP("RESTART RX ");
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|
337
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ssc_rx_stop();
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|
338
|
ssc_rx_mode_set(ssc_state.mode);
|
|
339
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ssc_rx_start();
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340
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led_toggle(1);
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341
|
break;
|
|
342
|
}
|
|
343
|
}
|
|
344
|
}
|
|
345
|
#endif
|
|
346
|
/* Ignore empty frames */
|
|
347
|
if (ssc_state.mode == SSC_MODE_CONTINUOUS) {
|
|
348
|
tmp = (uint32_t*)ssc_state.rx_ctx[0]->data + MAX_HDRSIZE;
|
|
349
|
emptyframe = 1;
|
|
350
|
for(i = (ssc_state.rx_ctx[0]->size-MAX_HDRSIZE) / 4 - 8/*WTF?*/; i > 0; i--) {
|
|
351
|
if( *tmp++ != 0xFFFFFFFF ) {
|
|
352
|
DEBUGPCR("NONEMPTY(%08x, %i): %08x", tmp, i, *(tmp-1));
|
|
353
|
emptyframe = 0;
|
|
354
|
break;
|
|
355
|
} else {
|
|
356
|
//DEBUGPCR("DUNNO(%08x, %i): %08x", tmp, i, tmp[i]);
|
|
357
|
}
|
|
358
|
}
|
|
359
|
}
|
|
360
|
//DEBUGP("Sending primary RCTX(%u, len=%u) ", req_ctx_num(ssc_state.rx_ctx[0]), ssc_state.rx_ctx[0]->tot_len);
|
|
361
|
/* Mark primary RCTX as ready to send for usb */
|
|
362
|
if(!emptyframe) {
|
|
363
|
DEBUGP("NONEMPTY");
|
|
364
|
req_ctx_set_state(ssc_state.rx_ctx[0],
|
|
365
|
RCTX_STATE_UDP_EP2_PENDING);
|
|
366
|
//RCTX_STATE_FREE);
|
|
367
|
} else {
|
|
368
|
DEBUGP("EMPTY");
|
|
369
|
req_ctx_put(ssc_state.rx_ctx[0]);
|
|
370
|
}
|
|
371
|
|
|
372
|
/* second buffer gets propagated to primary */
|
|
373
|
ssc_state.rx_ctx[0] = ssc_state.rx_ctx[1];
|
|
374
|
ssc_state.rx_ctx[1] = NULL;
|
|
375
|
if (ssc_sr & AT91C_SSC_RXBUFF) {
|
|
376
|
DEBUGP("RXBUFF! ");
|
|
377
|
if (ssc_state.rx_ctx[0]) {
|
|
378
|
//DEBUGP("Sending secondary RCTX(%u, len=%u) ", req_ctx_num(ssc_state.rx_ctx[0]), ssc_state.rx_ctx[0]->tot_len);
|
|
379
|
req_ctx_set_state(ssc_state.rx_ctx[0],
|
|
380
|
RCTX_STATE_UDP_EP2_PENDING);
|
|
381
|
//RCTX_STATE_FREE);
|
|
382
|
}
|
|
383
|
if (__ssc_rx_refill(0) == -1)
|
|
384
|
AT91F_SSC_DisableIt(ssc, AT91C_SSC_ENDRX |
|
|
385
|
AT91C_SSC_RXBUFF |
|
|
386
|
AT91C_SSC_OVRUN);
|
|
387
|
}
|
|
388
|
|
|
389
|
if (__ssc_rx_refill(1) == -1)
|
|
390
|
AT91F_SSC_DisableIt(ssc, AT91C_SSC_ENDRX |
|
|
391
|
AT91C_SSC_RXBUFF |
|
|
392
|
AT91C_SSC_OVRUN);
|
|
393
|
|
|
394
|
udp_refill_ep(2);
|
|
395
|
|
|
396
|
#if 0
|
|
397
|
if (__ssc_rx_refill(1) == -1)
|
|
398
|
AT91F_SSC_DisableIt(ssc, AT91C_SSC_ENDRX |
|
|
399
|
AT91C_SSC_RXBUFF |
|
|
400
|
AT91C_SSC_OVRUN);
|
|
401
|
#endif
|
|
402
|
}
|
|
403
|
|
|
404
|
if (ssc_sr & AT91C_SSC_OVRUN)
|
|
405
|
DEBUGP("RX_OVERRUN ");
|
|
406
|
|
|
407
|
if (ssc_sr & AT91C_SSC_CP0)
|
|
408
|
DEBUGP("CP0 ");
|
|
409
|
|
|
410
|
if (ssc_sr & AT91C_SSC_TXSYN)
|
|
411
|
DEBUGP("TXSYN ");
|
|
412
|
#if 0
|
|
413
|
led_toggle(1);
|
|
414
|
|
|
415
|
switch (ssc_state.mode) {
|
|
416
|
case SSC_MODE_14443A_SHORT:
|
|
417
|
if (ssc_sr & AT91C_SSC_RXSYN)
|
|
418
|
DEBUGP("RXSYN ");
|
|
419
|
if (ssc_sr & AT91C_SSC_RXRDY) {
|
|
420
|
uint32_t sample = ssc->SSC_RHR;
|
|
421
|
DEBUGP("RXRDY=0x%08x ", sample);
|
|
422
|
/* Try to set FDT compare register ASAP */
|
|
423
|
if (sample == REQA) {
|
|
424
|
tc_fdt_set(ISO14443A_FDT_SHORT_0);
|
|
425
|
/* FIXME: prepare and configure ATQA response */
|
|
426
|
} else if (sample == WUPA) {
|
|
427
|
tc_fdt_set(ISO14443A_FDT_SHORT_1);
|
|
428
|
/* FIXME: prepare and configure ATQA response */
|
|
429
|
} else
|
|
430
|
DEBUGP("<== unknown ");
|
|
431
|
}
|
|
432
|
break;
|
|
433
|
|
|
434
|
case SSC_MODE_14443A_STANDARD:
|
|
435
|
case SSC_MODE_EDGE_ONE_SHOT:
|
|
436
|
DEBUGP("ONE_SHOT ");
|
|
437
|
break;
|
|
438
|
default:
|
|
439
|
DEBUGP("UNKNOWN_MODE ");
|
|
440
|
break;
|
|
441
|
}
|
|
442
|
|
|
443
|
#endif
|
|
444
|
DEBUGPCR("I");
|
|
445
|
AT91F_AIC_ClearIt(AT91C_BASE_AIC, AT91C_ID_SSC);
|
|
446
|
}
|
|
447
|
|
|
448
|
void ssc_print(void)
|
|
449
|
{
|
|
450
|
DEBUGP("PDC_RPR=0x%08x ", rx_pdc->PDC_RPR);
|
|
451
|
DEBUGP("PDC_RCR=0x%08x ", rx_pdc->PDC_RCR);
|
|
452
|
DEBUGP("PDC_RNPR=0x%08x ", rx_pdc->PDC_RNPR);
|
|
453
|
DEBUGP("PDC_RNCR=0x%08x ", rx_pdc->PDC_RNCR);
|
|
454
|
}
|
|
455
|
|
|
456
|
|
|
457
|
void ssc_rx_unthrottle(void)
|
|
458
|
{
|
|
459
|
AT91F_SSC_EnableIt(ssc, AT91C_SSC_ENDRX | AT91C_SSC_CP0 |
|
|
460
|
AT91C_SSC_RXBUFF | AT91C_SSC_OVRUN);
|
|
461
|
}
|
|
462
|
|
|
463
|
void ssc_rx_start(void)
|
|
464
|
{
|
|
465
|
volatile int i;
|
|
466
|
//DEBUGPCRF("starting SSC RX\n");
|
|
467
|
|
|
468
|
/* Enable Reception */
|
|
469
|
AT91F_SSC_EnableIt(ssc, AT91C_SSC_ENDRX | AT91C_SSC_CP0 |
|
|
470
|
AT91C_SSC_RXBUFF | AT91C_SSC_OVRUN);
|
|
471
|
AT91F_SSC_EnableRx(AT91C_BASE_SSC);
|
|
472
|
|
|
473
|
/* Clear the flipflop */
|
|
474
|
tc_cdiv_sync_reset();
|
|
475
|
}
|
|
476
|
|
|
477
|
void ssc_rx_stop(void)
|
|
478
|
{
|
|
479
|
/* Disable reception */
|
|
480
|
AT91F_SSC_DisableRx(AT91C_BASE_SSC);
|
|
481
|
}
|
|
482
|
|
|
483
|
void ssc_tx_init(void)
|
|
484
|
{
|
|
485
|
/* IMPORTANT: Disable PA23 (PWM0) output, since it is connected to
|
|
486
|
* PA17 !! */
|
|
487
|
AT91F_PIO_CfgInput(AT91C_BASE_PIOA, OPENPCD_PIO_MFIN_PWM);
|
|
488
|
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, OPENPCD_PIO_MFIN_SSC_TX |
|
|
489
|
OPENPCD_PIO_MFOUT_SSC_RX | OPENPCD_PIO_SSP_CKIN |
|
|
490
|
AT91C_PIO_PA15, 0);
|
|
491
|
|
|
492
|
ssc_tx_mode_set(SSC_MODE_14443A_SHORT);
|
|
493
|
}
|
|
494
|
|
|
495
|
static int ssc_usb_in(struct req_ctx *rctx)
|
|
496
|
{
|
|
497
|
struct openpcd_hdr *poh = (struct openpcd_hdr *) rctx->data;
|
|
498
|
|
|
499
|
switch (poh->cmd) {
|
|
500
|
case OPENPCD_CMD_SSC_READ:
|
|
501
|
/* FIXME: allow host to specify mode */
|
|
502
|
ssc_rx_mode_set(SSC_MODE_EDGE_ONE_SHOT);
|
|
503
|
ssc_rx_start();
|
|
504
|
req_ctx_put(rctx);
|
|
505
|
return 0;
|
|
506
|
break;
|
|
507
|
case OPENPCD_CMD_SSC_WRITE:
|
|
508
|
/* FIXME: implement this */
|
|
509
|
//ssc_tx_start()
|
|
510
|
break;
|
|
511
|
default:
|
|
512
|
return USB_ERR(USB_ERR_CMD_UNKNOWN);
|
|
513
|
break;
|
|
514
|
}
|
|
515
|
|
|
516
|
return (poh->flags & OPENPCD_FLAG_RESPOND) ? USB_RET_RESPOND : 0;
|
|
517
|
}
|
|
518
|
|
|
519
|
void ssc_rx_init(void)
|
|
520
|
{
|
|
521
|
tc_cdiv_sync_init();
|
|
522
|
tc_cdiv_sync_enable();
|
|
523
|
|
|
524
|
rx_pdc = (AT91PS_PDC) &(ssc->SSC_RPR);
|
|
525
|
|
|
526
|
AT91F_SSC_CfgPMC();
|
|
527
|
|
|
528
|
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA,
|
|
529
|
OPENPCD_PIO_MFOUT_SSC_RX | OPENPCD_PIO_SSP_CKIN |
|
|
530
|
OPENPICC_PIO_FRAME,
|
|
531
|
0);
|
|
532
|
|
|
533
|
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPICC_PIO_SSC_DATA_CONTROL);
|
|
534
|
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, OPENPICC_PIO_SSC_DATA_CONTROL);
|
|
535
|
|
|
536
|
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SSC,
|
|
537
|
OPENPCD_IRQ_PRIO_SSC,
|
|
538
|
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &ssc_irq);
|
|
539
|
|
|
540
|
/* don't divide clock inside SSC, we do that in tc_cdiv */
|
|
541
|
ssc->SSC_CMR = 0;
|
|
542
|
|
|
543
|
#if 0
|
|
544
|
ssc->SSC_RCMR = AT91C_SSC_CKS_RK | AT91C_SSC_CKO_NONE |
|
|
545
|
AT91C_SSC_CKI | AT91C_SSC_START_CONTINOUS;
|
|
546
|
/* Data bits per Data N = 32-1
|
|
547
|
* Data words per Frame = 15-1 (=60 byte)*/
|
|
548
|
ssc->SSC_RFMR = 31 | AT91C_SSC_MSBF | (14 << 8);
|
|
549
|
#endif
|
|
550
|
|
|
551
|
__ssc_rx_refill(0);
|
|
552
|
__ssc_rx_refill(1);
|
|
553
|
|
|
554
|
ssc_rx_mode_set(SSC_MODE_NONE);
|
|
555
|
#if 0
|
|
556
|
AT91F_PDC_EnableRx(rx_pdc);
|
|
557
|
|
|
558
|
/* Enable RX interrupts */
|
|
559
|
AT91F_SSC_EnableIt(ssc, AT91C_SSC_OVRUN |
|
|
560
|
AT91C_SSC_ENDRX | AT91C_SSC_RXBUFF);
|
|
561
|
#endif
|
|
562
|
/* FIXME: This is hardcoded for REQA 0x26 */
|
|
563
|
tc_fdt_set(ISO14443A_FDT_SHORT_0);
|
|
564
|
|
|
565
|
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SSC);
|
|
566
|
|
|
567
|
//usb_hdlr_register(&ssc_usb_in, OPENPCD_CMD_CLS_SSC);
|
|
568
|
|
|
569
|
DEBUGP("\r\n");
|
|
570
|
}
|
|
571
|
|
|
572
|
void ssc_fini(void)
|
|
573
|
{
|
|
574
|
usb_hdlr_unregister(OPENPCD_CMD_CLS_SSC);
|
|
575
|
AT91F_PDC_DisableRx(rx_pdc);
|
|
576
|
AT91F_SSC_DisableTx(ssc);
|
|
577
|
AT91F_SSC_DisableRx(ssc);
|
|
578
|
AT91F_SSC_DisableIt(ssc, 0xfff);
|
|
579
|
AT91F_PMC_DisablePeriphClock(AT91C_BASE_PMC,
|
|
580
|
((unsigned int) 1 << AT91C_ID_SSC));
|
|
581
|
}
|
