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/* OpenPC TC (Timer / Clock) support code
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* (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This idea of this code is to feed the 13.56MHz carrier clock of RC632
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* into TCLK1, which is routed to XC1. Then configure TC0 to divide this
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* clock by a configurable divider.
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*
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*/
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#include <lib_AT91SAM7.h>
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#include <AT91SAM7.h>
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#include <os/dbgu.h>
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#include "../openpcd.h"
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#include <os/tc_cdiv.h>
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static AT91PS_TCB tcb = AT91C_BASE_TCB;
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/* set carrier divider to a specific */
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void tc_cdiv_set_divider(uint16_t div)
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{
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tcb->TCB_TC0.TC_RC = div;
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/* set to 50% duty cycle */
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tcb->TCB_TC0.TC_RA = 1;
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tcb->TCB_TC0.TC_RB = 1 + (div >> 1);
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}
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void tc_cdiv_phase_add(int16_t inc)
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{
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tcb->TCB_TC0.TC_RA = (tcb->TCB_TC0.TC_RA + inc) % tcb->TCB_TC0.TC_RC;
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tcb->TCB_TC0.TC_RB = (tcb->TCB_TC0.TC_RB + inc) % tcb->TCB_TC0.TC_RC;
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/* FIXME: can this be done more elegantly? */
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if (tcb->TCB_TC0.TC_RA == 0) {
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tcb->TCB_TC0.TC_RA += 1;
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tcb->TCB_TC0.TC_RB += 1;
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}
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}
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void tc_cdiv_init(void)
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{
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/* Cfg PA28(TCLK1), PA0(TIOA0), PA1(TIOB0), PA20(TCLK2) as Periph B */
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AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0,
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OPENPCD_PIO_CARRIER_IN |
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OPENPCD_PIO_CARRIER_DIV_OUT |
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OPENPCD_PIO_CDIV_HELP_OUT |
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OPENPCD_PIO_CDIV_HELP_IN);
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AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
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((unsigned int) 1 << AT91C_ID_TC0));
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/* Enable Clock for TC0 */
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tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN;
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/* Connect TCLK1 to XC1, TCLK2 to XC2 */
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tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC2XC2S);
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tcb->TCB_BMR |= (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC2XC2S_TCLK2);
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/* Clock XC1, Wave mode, Reset on RC comp
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* TIOA0 on RA comp = set, * TIOA0 on RC comp = clear,
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* TIOB0 on EEVT = set, TIOB0 on RB comp = clear,
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* EEVT = XC2 (TIOA0) */
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tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
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AT91C_TC_WAVESEL_UP_AUTO |
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AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR |
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AT91C_TC_BEEVT_SET | AT91C_TC_BCPB_CLEAR |
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AT91C_TC_EEVT_XC2 | AT91C_TC_ETRGEDG_RISING |
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AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR;
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tc_cdiv_set_divider(128);
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/* Reset to start timers */
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tcb->TCB_BCR = 1;
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}
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void tc_cdiv_print(void)
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{
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DEBUGP("TCB_BMR=0x%08x ", tcb->TCB_BMR);
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DEBUGP("TC0_CV=0x%08x ", tcb->TCB_TC0.TC_CV);
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DEBUGP("TC0_CMR=0x%08x ", tcb->TCB_TC0.TC_CMR);
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DEBUGPCR("TC0_SR=0x%08x", tcb->TCB_TC0.TC_SR);
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DEBUGPCR("TC0_RA=0x%04x, TC0_RB=0x%04x, TC0_RC=0x%04x",
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tcb->TCB_TC0.TC_RA, tcb->TCB_TC0.TC_RB, tcb->TCB_TC0.TC_RC);
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}
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void tc_cdiv_fini(void)
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{
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tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKDIS;
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AT91F_PMC_DisablePeriphClock(AT91C_BASE_PMC,
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((unsigned int) 1 << AT91C_ID_TC0));
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}
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