openpcd/firmware/include/openpicc_regs.h @ master
| 1 | 514b0f72 | laforge | #ifndef _OPENPICC_STATE
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| 2 | #define _OPENPICC_STATE
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| 3 | |||
| 4 | /* according to ISO 14443-3(2000) 6.2 */
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| 5 | enum opicc_14443a_state { |
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| 6 | ISO14443A_ST_POWEROFF, |
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| 7 | ISO14443A_ST_IDLE, |
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| 8 | ISO14443A_ST_READY, |
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| 9 | ISO14443A_ST_ACTIVE, |
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| 10 | ISO14443A_ST_HALT, |
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| 11 | ISO14443A_ST_READY2, |
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| 12 | ISO14443A_ST_ACTIVE2, |
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| 13 | };
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| 14 | |||
| 15 | enum opicc_reg_tx_control { |
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| 16 | OPICC_REG_TX_BPSK = 0x01, |
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| 17 | OPICC_REG_TX_MANCHESTER = 0x02, |
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| 18 | OPICC_REG_TX_INTENSITY0 = 0x00, |
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| 19 | OPICC_REG_TX_INTENSITY1 = 0x10, |
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| 20 | OPICC_REG_TX_INTENSITY2 = 0x20, |
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| 21 | OPICC_REG_TX_INTENSITY3 = 0x30, |
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| 22 | };
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| 23 | |||
| 24 | enum opicc_reg { |
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| 25 | OPICC_REG_14443A_UIDLEN,/* Length of UID in bytes */ |
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| 26 | |||
| 27 | OPICC_REG_14443A_FDT0, /* Frame delay time if last bit 0 */ |
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| 28 | OPICC_REG_14443A_FDT1, /* Frame delay time if last bit 1 */ |
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| 29 | OPICC_REG_14443A_STATE, /* see 'enum opicc_14443a_state' */ |
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| 30 | 28eb4a57 | laforge | OPICC_REG_14443A_ATQA, /* The ATQA template for 14443A */ |
| 31 | 514b0f72 | laforge | |
| 32 | OPICC_REG_RX_CLK_DIV, /* Clock divider for Rx sample clock */ |
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| 33 | OPICC_REG_RX_CLK_PHASE, /* Phase shift of Rx sample clock */ |
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| 34 | OPICC_REG_RX_COMP_LEVEL,/* Comparator level of Demodulator */ |
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| 35 | OPICC_REG_RX_CONTROL, |
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| 36 | |||
| 37 | OPICC_REG_TX_CLK_DIV, /* Clock divider for Tx sample clock */ |
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| 38 | OPICC_REG_TX_CONTROL, /* see 'enum opicc_reg_tx_Control */ |
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| 39 | _OPICC_NUM_REGS, |
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| 40 | };
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| 41 | |||
| 42 | enum openpicc_14443a_sregs { |
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| 43 | /* string 'registers' */
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| 44 | OPICC_REG_14443A_UID, /* The UID (4...10 bytes) */ |
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| 45 | };
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| 46 | |||
| 47 | #endif
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