DeTeWe ALIAN TSA » History » Version 3
laforge, 12/27/2023 01:04 PM
| 1 | 1 | laforge | h1. DeTeWe ALIAN TSA |
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| 3 | Part Number: H16B6058-J710 TSA-CE 28028 06A 003 / MADE IN AUSTRALIA |
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| 4 | Slot: 15+16 |
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| 6 | 2 | laforge | {{thumbnail(DSC00284.JPG,size=800)}} |
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| 8 | {{thumbnail(DSC00285.JPG,size=400)}} |
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| 9 | {{thumbnail(DSC00286.JPG,size=400)}} |
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| 11 | 3 | laforge | The TSA is the _Time Slot Assignment_ unit within the [[DeTeWe_ALIAN]] system. |
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| 13 | The functions fo the TSA are as follows: |
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| 14 | * Interchange timeslots between the two buses, in accordance with operator defined mapping tables |
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| 15 | • (The interchange function allows grooming of "like" services into common 2.048 Mb/s trunks) |
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| 16 | • Extend the tributary bus to up to 3 EXP shelves |
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| 17 | • Synchronize the internal clocks with the network clock |
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| 19 | 1 | laforge | h2. Hardware |
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| 21 | * 3x CY7C133-55JI 2kx16 dual-port SRAM |
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| 22 | * 46002-2032 TSA RXTX 6171-FD151 9806 JAPAN |
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| 23 | * 46002-2031 TSA RXRX 6172-FD151 9806 JAPAN |
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| 24 | * 46002-2030 TSA COMMON 6173-FD151 9809 JAPAN |
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| 25 | * 3x CY7B933-JI HOTLink receiver |
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| 26 | * 1x CY7B923-JI HOTLink transmitter |
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| 27 | * 3x MB81C10-30 1Mbit DRAM |
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| 28 | * MC68HC16Z1CPV16 uC |
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| 29 | * CY7C146 2x8k dual-port SRAM |
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| 30 | * 2x Motorola MC143150B1FB "Neuron Chip" |
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| 31 | ** ST M27C256 (IC7 H505 692-03) |
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| 32 | ** ST M27C256 (IC2 H505 691-04) |
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| 33 | ** 2x 29F040C-90 |
