GettingStarted » History » Revision 3
« Previous |
Revision 3/5
(diff)
| Next »
laforge, 02/19/2016 10:50 PM
= Firmware build =
- check out at91lib.git and osmo-sdr.git into the same ancestor directory
- change to osmo-sdr/firmware/sdr-test-project
- 'make flash'
- use rum-ba to flash it: * rumba /dev/ttyACM0 flashmcu osmo-sdr-test-osmo-sdr-at91sam3u4-flash.bin
= Firmware usage guide =
Serial consoleOn the serial console, you can enter three types of commands: * actions denoted by ! at the line end * getting a value, denoted by a ? at the line end * setting a value in key=value notation
A list of commands can be obtained by entering ? on an empty line
Enter always re-sets the parser, so you can abort any unfinished command with enter
=== Examples ===
{{{
> tuner.init!
> tuner.freq=88300000
> tuner.gain=2,2,2,2,2,2
> tuner.freq?
tuner.freq:88299997
}}}
=== Reference ===
{{{
?
Supported commands:
tuner.init -- Initialize the tuner
tuner.freq -- Tune to the specified frequency
tuner.gain -- Tune to the specified gain
tuner.flt_bw_mix -- Filter bandwidth (Mixer)
tuner.flt_bw_chan -- Filter bandwidth (Channel)
tuner.flt_bw_rc -- Filter bandwidth (RC)
si570.freq -- Change the SI570 clock frequency
si570.dump -- Dump SI570 registers
fpga.dump -- Dump FPGA registers
fpga.pwm1_div -- PWM divider, Freq = 80MHz/(div+1)
fpga.pwm1_duty -- PWM duty cycle
fpga.pwm2_div -- PWM divider, Freq = 80MHz/(div+1)
fpga.pwm2_duty -- PWM duty cycle
fpga.adc_clkdiv -- FPGA Clock Divider for ADC (80 MHz/CLKDIV)
fpga.adc_acqlen -- Num of SCK cycles nCS to AD7357 is held high betewen conversions
ssc.start -- Start the SSC Receiver
ssc.stop -- Start the SSC Receiver
ssc.stats -- Statistics about the SSC
ssc.dump -- Dump SSC DMA registers
}}}
1. connect the device to usb, it should enumerate as usb audio device
1. connect to the UART
1. issue the following commands once
1. {{{tuner.init!}}}
1. {{{tuner.freq=88300000}}}
1. start your audio recording app, e.g. {{{arecord -c 2 -f S16_LE -D hw:1,0 foo.wav}}}
You can re-tune the frequency and/or issue other commands while the transfer of samples is running.
The bottom green led under the antenna socket should be dark green, not completely off.
Updated by laforge about 8 years ago · 3 revisions