osmo-sdr/fpga/hw-v2/compile.cfg @ master
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[View] |
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Entity= |
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Architecture= |
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TopLevelType= |
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[file:.\src\usbrx\toplevel\usbrx_toplevel.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\toplevel\usbrx_clkgen.vhd] |
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Enabled=1 |
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[file:.\src\mt_toolbox\mt_toolbox.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\toplevel\usbrx_spi.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\toplevel\usbrx_regbank.vhd] |
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Enabled=1 |
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[file:.\src\testbench\tb_usbrx.vhd] |
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Enabled=1 |
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VerilogLanguage=7 |
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LIB= |
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[file:.\src\usbrx\toplevel\usbrx_pwm.vhd] |
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Enabled=1 |
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[file:.\src\mt_filter\mt_filter.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\filter\usbrx_halfband.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\datapath\usbrx_decimate.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\datapath\usbrx_ad7357.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\datapath\usbrx_ssc.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\usbrx.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\datapath\usbrx_offset.vhd] |
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Enabled=1 |
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[file:.\src\mt_filter\mt_fil_storage_slow.vhd] |
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Enabled=1 |
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[file:.\src\mt_filter\mt_fil_mac_slow.vhd] |
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Enabled=1 |
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[file:.\src\mt_filter\mt_fir_symmetric_slow.vhd] |
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Enabled=1 |
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[file:.\src\mt_toolbox\mt_clktools.vhd] |
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Enabled=1 |
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[file:.\src\testbench\tb_filter.vhd] |
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LIB= |
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Enabled=1 |
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VerilogLanguage=7 |
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[file:.\src\usbrx\toplevel\usbrx_clkref.vhd] |
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Enabled=1 |
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[file:.\src\mt_toolbox\mt_synctools.vhd] |
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Enabled=1 |
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[file:.\src\usbrx\toplevel\usbrx_gpio.vhd] |
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Enabled=1 |