osmo-sdr/fpga/hw-v2/bde.set @ master
| 1 |
########## |
|---|---|
| 2 |
BUS DEFAULT NAME |
| 3 |
BUS |
| 4 |
########## |
| 5 |
BUS DEFAULT TYPE |
| 6 |
STD_LOGIC_VECTOR |
| 7 |
########## |
| 8 |
BUS GLOBAL CONNECTOR |
| 9 |
GlobalBus |
| 10 |
########## |
| 11 |
BUS INDEX END |
| 12 |
0 |
| 13 |
########## |
| 14 |
BUS INDEX START |
| 15 |
7 |
| 16 |
########## |
| 17 |
BUS TERMINAL BUFFER |
| 18 |
BusBuffer |
| 19 |
########## |
| 20 |
BUS TERMINAL IN |
| 21 |
BusInput |
| 22 |
########## |
| 23 |
BUS TERMINAL INOUT |
| 24 |
BusBidirectional |
| 25 |
########## |
| 26 |
BUS TERMINAL OUT |
| 27 |
BusOutput |
| 28 |
########## |
| 29 |
CHECK DIAGRAM |
| 30 |
YES |
| 31 |
########## |
| 32 |
DEFAULT BDE LANGUAGE |
| 33 |
VHDL |
| 34 |
########## |
| 35 |
FILE HEADER |
| 36 |
-- |
| 37 |
-- file <GENERATEDFILE> |
| 38 |
-- generated <TIME> |
| 39 |
-- from <SOURCEFILE> |
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-- by <GENERATORVERSION> |
| 41 |
-- |
| 42 |
########## |
| 43 |
GLOBAL CONNECTOR |
| 44 |
Global |
| 45 |
########## |
| 46 |
GND DEFAULT TYPE |
| 47 |
STD_LOGIC |
| 48 |
########## |
| 49 |
GND DEFAULT VALUE |
| 50 |
'0' |
| 51 |
########## |
| 52 |
HANGING WIRE DEFAULT TYPE |
| 53 |
STD_LOGIC |
| 54 |
########## |
| 55 |
HANGING WIRE DEFAULT VALUE |
| 56 |
'Z' |
| 57 |
########## |
| 58 |
INCLUDE ACTIVE LIBRARY CLAUSE |
| 59 |
0 |
| 60 |
########## |
| 61 |
INCREMENT NET FACTOR |
| 62 |
1 |
| 63 |
########## |
| 64 |
INCREMENT NET START |
| 65 |
0 |
| 66 |
########## |
| 67 |
INCREMENT NETS |
| 68 |
0 |
| 69 |
########## |
| 70 |
LIBRARIES |
| 71 |
library IEEE; |
| 72 |
use IEEE.std_logic_1164.all; |
| 73 |
########## |
| 74 |
TERMINAL BUFFER |
| 75 |
Buffer |
| 76 |
########## |
| 77 |
TERMINAL IN |
| 78 |
Input |
| 79 |
########## |
| 80 |
TERMINAL INOUT |
| 81 |
Bidirectional |
| 82 |
########## |
| 83 |
TERMINAL OUT |
| 84 |
Output |
| 85 |
########## |
| 86 |
USE GLOBAL DEFAULTS |
| 87 |
1 |
| 88 |
########## |
| 89 |
VCC DEFAULT TYPE |
| 90 |
STD_LOGIC |
| 91 |
########## |
| 92 |
VCC DEFAULT VALUE |
| 93 |
'1' |
| 94 |
########## |
| 95 |
VERILOG DANGLING DEFAULT VALUE |
| 96 |
1'bZ |
| 97 |
########## |
| 98 |
VERILOG DESIGN UNIT HEADER |
| 99 |
`timescale 1ps / 1ps |
| 100 |
########## |
| 101 |
VERILOG FILE HEADER |
| 102 |
// |
| 103 |
// file <GENERATEDFILE> |
| 104 |
// generated <TIME> |
| 105 |
// from <SOURCEFILE> |
| 106 |
// by <GENERATORVERSION> |
| 107 |
// |
| 108 |
########## |
| 109 |
VERILOG GND DEFAULT TYPE |
| 110 |
supply0 |
| 111 |
########## |
| 112 |
VERILOG GND DEFAULT VALUE |
| 113 |
1'b0 |
| 114 |
########## |
| 115 |
VERILOG VCC DEFAULT TYPE |
| 116 |
supply1 |
| 117 |
########## |
| 118 |
VERILOG VCC DEFAULT VALUE |
| 119 |
1'b1 |
| 120 |
########## |
| 121 |
WIRE DEFAULT NAME |
| 122 |
NET |
| 123 |
########## |
| 124 |
WIRE DEFAULT TYPE |
| 125 |
STD_LOGIC |
