Hardware Projects » OpenVizsla USB tracer/analyzer

Those THT header's drill diameter is 0,9mm, for them a relaxed DRC would accept restrings not smaller than 0,254mm. In the current OV design they are 0,3mm, however, if they get drilled off-center (like on mine OV, see images), they end up being smaller than needed. The switch SW1 has drills of 1mm and a restring of 0,5mm which generally leaves more freedom when soldered by hand. So 0,5mm also for the pin header would be nice if no other clearance issues arise from this: the shown wire trace in the middle of the double-row header could be moved away, but on the top side of e.g. header P4 maintaining clearance might be more work.

Alternativly, IIRC, Altium allows to define different annular ring sizes for top-mid-bottom layers, so maybe for the bottom layer, a 0,5mm setting would be nice, where for the top (as well as for the inner) layer the 0,3mm setting could remain.

You're correct that it's possible to change the pad sizes on a per-layer basis. Increasing just the bottom pad size to have a .5mm annular ring requires no layout changes, so it's a quick solution.

Fixed in: https://github.com/openvizsla/ov_ftdi/pull/46/commits/8f46340678c33d52b66a5e50ca84fc8d6ddb2a0d

OK, nice - but please ease the situation with that power wire shown there like you solved it with VBUS elsewhere.

Sure, I'll move it. Is it possible to state this in a more concrete fashion, so I can make a DRC rule? Something like a minimum spacing between power-class nets and thru-hole pads? I'm assuming the goal here is to decrease the chance of an assembly error during hand soldering. It's not totally clear to me the difference between this situation and the many smaller (data) traces that are routed through the pads on that connector.

For reference, the standard clearance on the board is 6 mils.

Hopefully improved here: https://github.com/openvizsla/ov_ftdi/pull/46/commits/79dc1ebf1482506938d3722ed482db7fb99cddec

works for me, thanks!