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Revision 3 (Anonymous, 02/19/2016 10:52 PM) → Revision 4/6 (Anonymous, 02/19/2016 10:52 PM)
= UmTRX architecture = The LMS6002D FPRF ICs provide analogue filtering, VGAs, VCOs and mixers etc. in addition to performing digital conversion. DC offset and IQ balance correction A typical SDR architecture is implemented in the front-end in the FPGA. Host connection is via gigabit Ethernet and samples along with timestamps and system settings such as frequency, gain and bandwidth, are encapsulated in [http://www.vita.com/home/Specification/Specifications.html VITA Radio Transport] (VRT) packets. Higher employed, whereby higher TX and RX sample rates are used in the front-end than in communication with the host, and host. This is made possible by half-band and CIC filters that are implemented in inside the FPGA are used to FPGA, and which perform up/down-conversion, up/down-conversion and thereby shift the frequency within the original sample rate, with amplitude correction in place pre (RX) and post (TX) filtering. This allows the frequency to be shifted within the original sample rate and without having to re-tune the LMS6002D transceiver. After filtering, RX samples are stuffed into VITA Radio Transport (VRT) packets and immediately forwarded to the host by the Ethernet packet router. On the TX side, packets received from the host are buffered by first placed into a SRAM FIFO to help ensure FIFO, which buffers samples so that there are we always samples have something to transmit. send. RX samples are time-stamped and TX samples can be sent at a precise time, ensuring that TX and RX are perfectly aligned (this is critical for TDM systems). DC offset and IQ balance correction is implemented in the signal chain front-end in the FPGA. The LMS6002D ICs provide analogue filtering, VGAs, VCOs and mixers etc. in addition to performing digital conversion. == High level == [[Image(UmTRX.png,75%)]] == FPGA == [[Image(FPGA_structure.png,50%)]]
