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1
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from analog: SSC_DATA, CARRIER (via PLL)
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2
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to analog: MOD
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3
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4
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MOD on PA17 (SSC TD, out), PA23 (PWM0, out)
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5
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SSC_DATA on PA18 (SSC RD, in), PA27 (TIOB2, in)
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6
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FRAME on PA20 (SSC RF, in)
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7
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8
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CARRIER (T5) on PA28 (TCLK1, in)
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9
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CARRIER_DIV_HELP (T3) on PA0 (TIOA0, out), PA29 (TCLK2, in)
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10
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(TF) on PA26 (TIOA2, out), PA15 (SSC TF, in)
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11
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12
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SSC_CLOCK (T4) on PA1 (TIOB0, out), PA19 (SSC RK, in)
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13
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14
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15
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MOD: pure output, to modulation circuitry
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16
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* either fed from SSC transmitter
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17
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* or fed from PWM
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18
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SSC_DATA: pure input, from demulation circuitry
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19
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* goes to SSC receiver
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20
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* goes to tc_fdt as external event (TIOB2)
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21
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FRAME: set on any edge in SSC_DATA, reset by SSC_DATA_CONTROL (out)
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22
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* goes to SSC receiver as frame signal
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23
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24
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CARRIER: pure input, from PLL
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25
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* goes to tc_cdiv and tc_fdt as XC1 (TCLK1)
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26
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CARRIER_DIV_HELP: internal signal, does ???
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27
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* comes from tc_cdiv (TIOA0)
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28
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* goes to tc_cdiv as XC2 (TCLK2)
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29
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TF: internal signal, transmission start
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30
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* comes from tc_fdt (TIOA2)
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31
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* goes to SSC transmitter as frame signal
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32
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33
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SSC_CLOCK: internal signal, transceiver clock
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34
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* comes from tc_cdiv (TIOB0)
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35
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* goes to SSC transmitter and receiver as clock signal
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36
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37
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tc_cdiv: XC1=TCLK1 (in), TIOB0 (out), TIOA0 (out), XC2=TCLK2 (in)
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38
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TC0 enabled
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39
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XC1 = TCLK1, XC2 = TCLK2
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40
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TC0: Clock from XC1, Wave mode, WAVSEL=2 (up auto)
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41
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TIOA0: RA compare = set, RC compare = clear, swtrg = clear
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42
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TIOB0: eevent = set, RB compare = clear, swtrg = clear
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43
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eevent: XC2, external trigger on rising edge
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44
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RA = 1, RB = 1 + divider/2, RC = divider
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45
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46
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i.o.w: when CV = 0 (either through swtrg or through RC compare) then TIOA0 and TIOB0 are clear
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47
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TIOA0 is set on RA compare (at CV=1+phase), is connected to XC2 (through TCLK2) and therefore triggers the external event which sets TIOB0
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48
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TIOB0 is cleared at RB compare (at CV=1+divider/2+phase)
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49
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that means: Compare A sets TIOB and Compare B clears TIOB, Compare C is fixed at the divisor value, Compare A and B are divisor/2 apart, yielding an exact 50% duty cycle with a variable phase shift (offset from CV=0)
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50
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this trick is necessary because TIO{A,B} can't be directly affected by Compare {B,A}, so when using only one TIO you can either get a fixed duty cycle with zero offset compared to CV=0, or a variable offset yielding a variable duty cycle
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51
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52
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tc_fdt: TIOA2 (out), TIOB2 (in), XC1=TCLK1 (in)
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53
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TC2 enabled
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54
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TC2: Clock from XC1, Wave mode, WAVSEL=0 (up)
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55
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TIOA2: RA compare = set, RC compare = clear, eevent = clear
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56
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TIOB2: eevent = nothing, RB compare = nothing
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57
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eevent: TIOB2, external trigger on falling edge, clock started and enabled on external trigger
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58
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clock stopped on RC compare
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59
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RC = 0xffff, RB = frame_end_set, RA = fdt_set
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60
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61
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