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/* Synchronize TC_CDIV divided sample clock with the SOF of the packet */
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#include <lib_AT91SAM7.h>
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#include <AT91SAM7.h>
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#include "tc_cdiv_sync.h"
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#include "dbgu.h"
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#include "pio_irq.h"
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#include "openpicc.h"
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#include "led.h"
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#include "tc_cdiv.h"
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#define USE_IRQ
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static u_int8_t enabled;
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static void pio_data_change(u_int32_t pio)
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{
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(void)pio;
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DEBUGP("PIO_FRAME_IRQ: ");
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/* we get one interrupt for each change. If now, after the
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* change the level is high, then it must have been a rising
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* edge */
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if (*AT91C_PIOA_PDSR & OPENPICC_PIO_FRAME) {
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vLedSetGreen(1);
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/* This code is now replaced by hard-coded assembler code in os/boot/boot.s my_fiq_handler */
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/* *AT91C_TC0_CCR = AT91C_TC_SWTRG;*/
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DEBUGPCR("CDIV_SYNC_FLIP SWTRG CV=0x%08x",
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*AT91C_TC0_CV);
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vLedSetGreen(0);
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} else
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DEBUGPCR("");
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//vLedSetGreen(0);
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}
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void tc_cdiv_sync_reset(void)
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{
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if (enabled) {
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u_int32_t tmp = *AT91C_PIOA_ISR;
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(void)tmp;
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volatile int i;
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DEBUGPCRF("CDIV_SYNC_FLOP");
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//vLedSetGreen(1);
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/* reset the hardware flipflop, this clears FRAME */
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AT91F_PIO_ClearOutput(AT91C_BASE_PIOA,
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OPENPICC_PIO_SSC_DATA_CONTROL);
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for (i = 0; i < 0xff; i++) ;
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AT91F_PIO_SetOutput(AT91C_BASE_PIOA,
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OPENPICC_PIO_SSC_DATA_CONTROL);
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if(OPENPICC->features.clock_gating) {
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/* reset tc_cdiv counter, the cleared frame signal stopped the tc_cdiv clock */
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tc_cdiv_reset();
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}
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}
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}
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void tc_cdiv_sync_disable(void)
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{
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enabled = 0;
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*AT91C_PIOA_IDR = OPENPICC_PIO_FRAME;
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}
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void tc_cdiv_sync_enable(void)
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{
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enabled = 1;
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DEBUGPCRF("CDIV_SYNC_ENABLE ");
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tc_cdiv_sync_reset();
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*AT91C_PIOA_IER = OPENPICC_PIO_FRAME;
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}
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void tc_cdiv_sync_init()
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{
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pio_irq_init_once();
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DEBUGPCRF("initializing");
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enabled = 0;
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AT91F_PIOA_CfgPMC();
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AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPICC_PIO_SSC_DATA_CONTROL);
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/* This code is now replaced by hard-coded assembler code in os/boot/boot.s my_fiq_handler */
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/*pio_irq_register(OPENPICC_PIO_FRAME, &pio_data_change);*/
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(void)pio_data_change;
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//vLedSetGreen(0);
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tc_cdiv_sync_disable();
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}
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