openpcd/openpcd/pll.txt @ master
| 1 |
MAINCLK = 18.432MHz |
|---|---|
| 2 |
PLLCLK(div=24,mul=125) = 96MHz |
| 3 |
MCLK(divisor 2) = 48MHz |
| 4 |
USB(divisor 2) = 48MHz |
| 5 |
MC_FWR(FWS) = 2 # 1 flash waitstate |
| 6 |
|
| 7 |
SPCK(SCBR=10) = 4.8MHz # 5MHz max clock RC632 |
