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//* ----------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//* ----------------------------------------------------------------------------
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//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//* ----------------------------------------------------------------------------
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//* File Name : lib_AT91SAM7S64.h
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//* Object : AT91SAM7S64 inlined functions
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//* Generated : AT91 SW Application Group 08/30/2005 (15:52:59)
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//*
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//* CVS Reference : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005//
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//* CVS Reference : /lib_pmc_SAM7S.h/1.4/Tue Aug 30 13:00:43 2005//
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//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
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//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
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//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
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//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
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//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
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//* CVS Reference : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005//
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//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
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//* CVS Reference : /lib_aic_6075b.h/1.2/Thu Jul 7 07:48:22 2005//
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//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
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//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
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//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
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//* CVS Reference : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005//
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//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
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//* CVS Reference : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004//
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//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
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//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
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//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
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//* ----------------------------------------------------------------------------
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#ifndef lib_AT91SAM7S64_H
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#define lib_AT91SAM7S64_H
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#include <AT91SAM7.h>
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/* *****************************************************************************
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SOFTWARE API FOR AIC
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***************************************************************************** */
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#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_ConfigureIt
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//* \brief Interrupt Handler Initialization
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//*----------------------------------------------------------------------------
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extern unsigned int AT91F_AIC_ConfigureIt (
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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unsigned int irq_id, // \arg interrupt number to initialize
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unsigned int priority, // \arg priority to give to the interrupt
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unsigned int src_type, // \arg activation and sense of activation
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void (*newHandler) () ); // \arg address of the interrupt handler
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_EnableIt
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//* \brief Enable corresponding IT number
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//*----------------------------------------------------------------------------
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static inline void AT91F_AIC_EnableIt (
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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unsigned int irq_id ) // \arg interrupt number to initialize
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{
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//* Enable the interrupt on the interrupt controller
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pAic->AIC_IECR = 0x1 << irq_id ;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_DisableIt
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//* \brief Disable corresponding IT number
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//*----------------------------------------------------------------------------
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static inline void AT91F_AIC_DisableIt (
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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unsigned int irq_id ) // \arg interrupt number to initialize
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{
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unsigned int mask = 0x1 << irq_id;
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//* Disable the interrupt on the interrupt controller
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pAic->AIC_IDCR = mask ;
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//* Clear the interrupt on the Interrupt Controller ( if one is pending )
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pAic->AIC_ICCR = mask ;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_ClearIt
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//* \brief Clear corresponding IT number
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//*----------------------------------------------------------------------------
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static inline void AT91F_AIC_ClearIt (
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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unsigned int irq_id) // \arg interrupt number to initialize
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{
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//* Clear the interrupt on the Interrupt Controller ( if one is pending )
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pAic->AIC_ICCR = (0x1 << irq_id);
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_AcknowledgeIt
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//* \brief Acknowledge corresponding IT number
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//*----------------------------------------------------------------------------
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static inline void AT91F_AIC_AcknowledgeIt (
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AT91PS_AIC pAic) // \arg pointer to the AIC registers
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{
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pAic->AIC_EOICR = pAic->AIC_EOICR;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_SetExceptionVector
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//* \brief Configure vector handler
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//*----------------------------------------------------------------------------
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extern unsigned int AT91F_AIC_SetExceptionVector (
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unsigned int *pVector, // \arg pointer to the AIC registers
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void (*Handler) () ); // \arg Interrupt Handler
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_Trig
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//* \brief Trig an IT
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//*----------------------------------------------------------------------------
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static inline void AT91F_AIC_Trig (
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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unsigned int irq_id) // \arg interrupt number
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{
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pAic->AIC_ISCR = (0x1 << irq_id) ;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_IsActive
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//* \brief Test if an IT is active
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//*----------------------------------------------------------------------------
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static inline unsigned int AT91F_AIC_IsActive (
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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unsigned int irq_id) // \arg Interrupt Number
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{
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return (pAic->AIC_ISR & (0x1 << irq_id));
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_IsPending
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//* \brief Test if an IT is pending
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//*----------------------------------------------------------------------------
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static inline unsigned int AT91F_AIC_IsPending (
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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unsigned int irq_id) // \arg Interrupt Number
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{
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return (pAic->AIC_IPR & (0x1 << irq_id));
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_AIC_Open
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//* \brief Set exception vectors and AIC registers to default values
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//*----------------------------------------------------------------------------
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extern void AT91F_AIC_Open(
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AT91PS_AIC pAic, // \arg pointer to the AIC registers
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void (*IrqHandler) (), // \arg Default IRQ vector exception
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void (*FiqHandler) (), // \arg Default FIQ vector exception
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void (*DefaultHandler) (), // \arg Default Handler set in ISR
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void (*SpuriousHandler) (), // \arg Default Spurious Handler
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unsigned int protectMode); // \arg Debug Control Register
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/* *****************************************************************************
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SOFTWARE API FOR PDC
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***************************************************************************** */
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_SetNextRx
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//* \brief Set the next receive transfer descriptor
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_SetNextRx (
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AT91PS_PDC pPDC, // \arg pointer to a PDC controller
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unsigned char *address,// \arg address to the next bloc to be received
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unsigned int bytes) // \arg number of bytes to be received
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{
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pPDC->PDC_RNPR = (unsigned int) address;
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pPDC->PDC_RNCR = bytes;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_SetNextTx
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//* \brief Set the next transmit transfer descriptor
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_SetNextTx (
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AT91PS_PDC pPDC, // \arg pointer to a PDC controller
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const unsigned char *address,// \arg address to the next bloc to be transmitted
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unsigned int bytes) // \arg number of bytes to be transmitted
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{
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pPDC->PDC_TNPR = (unsigned int) address;
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pPDC->PDC_TNCR = bytes;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_SetRx
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//* \brief Set the receive transfer descriptor
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_SetRx (
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AT91PS_PDC pPDC, // \arg pointer to a PDC controller
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unsigned char *address,// \arg address to the next bloc to be received
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unsigned int bytes) // \arg number of bytes to be received
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{
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pPDC->PDC_RPR = (unsigned int) address;
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pPDC->PDC_RCR = bytes;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_SetTx
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//* \brief Set the transmit transfer descriptor
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_SetTx (
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AT91PS_PDC pPDC, // \arg pointer to a PDC controller
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const unsigned char *address,// \arg address to the next bloc to be transmitted
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unsigned int bytes) // \arg number of bytes to be transmitted
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{
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pPDC->PDC_TPR = (unsigned int) address;
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pPDC->PDC_TCR = bytes;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_EnableTx
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//* \brief Enable transmit
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_EnableTx (
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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{
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pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_EnableRx
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//* \brief Enable receive
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_EnableRx (
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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{
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pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_DisableTx
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//* \brief Disable transmit
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_DisableTx (
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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{
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pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_DisableRx
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//* \brief Disable receive
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//*----------------------------------------------------------------------------
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static inline void AT91F_PDC_DisableRx (
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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{
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pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
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}
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_IsTxEmpty
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//* \brief Test if the current transfer descriptor has been sent
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//*----------------------------------------------------------------------------
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static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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{
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return !(pPDC->PDC_TCR);
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}
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268
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_IsNextTxEmpty
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//* \brief Test if the next transfer descriptor has been moved to the current td
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//*----------------------------------------------------------------------------
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static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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{
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return !(pPDC->PDC_TNCR);
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}
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//*----------------------------------------------------------------------------
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279
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//* \fn AT91F_PDC_IsRxEmpty
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//* \brief Test if the current transfer descriptor has been filled
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//*----------------------------------------------------------------------------
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282
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static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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284
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{
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285
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return !(pPDC->PDC_RCR);
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}
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288
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//*----------------------------------------------------------------------------
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//* \fn AT91F_PDC_IsNextRxEmpty
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//* \brief Test if the next transfer descriptor has been moved to the current td
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291
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//*----------------------------------------------------------------------------
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292
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static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
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AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
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294
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{
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295
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return !(pPDC->PDC_RNCR);
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296
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}
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297
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298
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//*----------------------------------------------------------------------------
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299
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//* \fn AT91F_PDC_Open
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//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
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301
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//*----------------------------------------------------------------------------
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302
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extern void AT91F_PDC_Open(AT91PS_PDC pPDC); // \arg pointer to a PDC controller
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303
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304
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//*----------------------------------------------------------------------------
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305
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//* \fn AT91F_PDC_Close
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306
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//* \brief Close PDC: disable TX and RX reset transfer descriptors
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307
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//*----------------------------------------------------------------------------
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308
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extern void AT91F_PDC_Close(AT91PS_PDC pPDC); // \arg pointer to a PDC controller
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309
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310
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//*----------------------------------------------------------------------------
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311
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//* \fn AT91F_PDC_SendFrame
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312
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//* \brief Close PDC: disable TX and RX reset transfer descriptors
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313
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//*----------------------------------------------------------------------------
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314
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extern unsigned int AT91F_PDC_SendFrame(
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315
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AT91PS_PDC pPDC,
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316
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const unsigned char *pBuffer,
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317
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unsigned int szBuffer,
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318
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const unsigned char *pNextBuffer,
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319
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unsigned int szNextBuffer);
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320
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321
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//*----------------------------------------------------------------------------
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322
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//* \fn AT91F_PDC_ReceiveFrame
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323
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//* \brief Close PDC: disable TX and RX reset transfer descriptors
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324
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//*----------------------------------------------------------------------------
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325
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extern unsigned int AT91F_PDC_ReceiveFrame (
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326
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AT91PS_PDC pPDC,
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327
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unsigned char *pBuffer,
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328
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unsigned int szBuffer,
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329
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unsigned char *pNextBuffer,
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330
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unsigned int szNextBuffer);
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331
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332
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/* *****************************************************************************
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333
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SOFTWARE API FOR DBGU
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334
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***************************************************************************** */
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335
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//*----------------------------------------------------------------------------
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336
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//* \fn AT91F_DBGU_InterruptEnable
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|
337
|
//* \brief Enable DBGU Interrupt
|
|
338
|
//*----------------------------------------------------------------------------
|
|
339
|
static inline void AT91F_DBGU_InterruptEnable(
|
|
340
|
AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
|
|
341
|
unsigned int flag) // \arg dbgu interrupt to be enabled
|
|
342
|
{
|
|
343
|
pDbgu->DBGU_IER = flag;
|
|
344
|
}
|
|
345
|
|
|
346
|
//*----------------------------------------------------------------------------
|
|
347
|
//* \fn AT91F_DBGU_InterruptDisable
|
|
348
|
//* \brief Disable DBGU Interrupt
|
|
349
|
//*----------------------------------------------------------------------------
|
|
350
|
static inline void AT91F_DBGU_InterruptDisable(
|
|
351
|
AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
|
|
352
|
unsigned int flag) // \arg dbgu interrupt to be disabled
|
|
353
|
{
|
|
354
|
pDbgu->DBGU_IDR = flag;
|
|
355
|
}
|
|
356
|
|
|
357
|
//*----------------------------------------------------------------------------
|
|
358
|
//* \fn AT91F_DBGU_GetInterruptMaskStatus
|
|
359
|
//* \brief Return DBGU Interrupt Mask Status
|
|
360
|
//*----------------------------------------------------------------------------
|
|
361
|
static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
|
|
362
|
AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
|
|
363
|
{
|
|
364
|
return pDbgu->DBGU_IMR;
|
|
365
|
}
|
|
366
|
|
|
367
|
//*----------------------------------------------------------------------------
|
|
368
|
//* \fn AT91F_DBGU_IsInterruptMasked
|
|
369
|
//* \brief Test if DBGU Interrupt is Masked
|
|
370
|
//*----------------------------------------------------------------------------
|
|
371
|
static inline int AT91F_DBGU_IsInterruptMasked(
|
|
372
|
AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
|
|
373
|
unsigned int flag) // \arg flag to be tested
|
|
374
|
{
|
|
375
|
return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
|
|
376
|
}
|
|
377
|
|
|
378
|
/* *****************************************************************************
|
|
379
|
SOFTWARE API FOR PIO
|
|
380
|
***************************************************************************** */
|
|
381
|
//*----------------------------------------------------------------------------
|
|
382
|
//* \fn AT91F_PIO_CfgPeriph
|
|
383
|
//* \brief Enable pins to be drived by peripheral
|
|
384
|
//*----------------------------------------------------------------------------
|
|
385
|
static inline void AT91F_PIO_CfgPeriph(
|
|
386
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
387
|
unsigned int periphAEnable, // \arg PERIPH A to enable
|
|
388
|
unsigned int periphBEnable) // \arg PERIPH B to enable
|
|
389
|
|
|
390
|
{
|
|
391
|
pPio->PIO_ASR = periphAEnable;
|
|
392
|
pPio->PIO_BSR = periphBEnable;
|
|
393
|
pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
|
|
394
|
}
|
|
395
|
|
|
396
|
//*----------------------------------------------------------------------------
|
|
397
|
//* \fn AT91F_PIO_CfgOutput
|
|
398
|
//* \brief Enable PIO in output mode
|
|
399
|
//*----------------------------------------------------------------------------
|
|
400
|
static inline void AT91F_PIO_CfgOutput(
|
|
401
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
402
|
unsigned int pioEnable) // \arg PIO to be enabled
|
|
403
|
{
|
|
404
|
pPio->PIO_PER = pioEnable; // Set in PIO mode
|
|
405
|
pPio->PIO_OER = pioEnable; // Configure in Output
|
|
406
|
}
|
|
407
|
|
|
408
|
//*----------------------------------------------------------------------------
|
|
409
|
//* \fn AT91F_PIO_CfgInput
|
|
410
|
//* \brief Enable PIO in input mode
|
|
411
|
//*----------------------------------------------------------------------------
|
|
412
|
static inline void AT91F_PIO_CfgInput(
|
|
413
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
414
|
unsigned int inputEnable) // \arg PIO to be enabled
|
|
415
|
{
|
|
416
|
// Disable output
|
|
417
|
pPio->PIO_ODR = inputEnable;
|
|
418
|
pPio->PIO_PER = inputEnable;
|
|
419
|
}
|
|
420
|
|
|
421
|
//*----------------------------------------------------------------------------
|
|
422
|
//* \fn AT91F_PIO_CfgOpendrain
|
|
423
|
//* \brief Configure PIO in open drain
|
|
424
|
//*----------------------------------------------------------------------------
|
|
425
|
static inline void AT91F_PIO_CfgOpendrain(
|
|
426
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
427
|
unsigned int multiDrvEnable) // \arg pio to be configured in open drain
|
|
428
|
{
|
|
429
|
// Configure the multi-drive option
|
|
430
|
pPio->PIO_MDDR = ~multiDrvEnable;
|
|
431
|
pPio->PIO_MDER = multiDrvEnable;
|
|
432
|
}
|
|
433
|
|
|
434
|
//*----------------------------------------------------------------------------
|
|
435
|
//* \fn AT91F_PIO_CfgPullup
|
|
436
|
//* \brief Enable pullup on PIO
|
|
437
|
//*----------------------------------------------------------------------------
|
|
438
|
static inline void AT91F_PIO_CfgPullup(
|
|
439
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
440
|
unsigned int pullupEnable) // \arg enable pullup on PIO
|
|
441
|
{
|
|
442
|
// Connect or not Pullup
|
|
443
|
pPio->PIO_PPUDR = ~pullupEnable;
|
|
444
|
pPio->PIO_PPUER = pullupEnable;
|
|
445
|
}
|
|
446
|
|
|
447
|
static inline void AT91F_PIO_CfgPullupEn(
|
|
448
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
449
|
unsigned int pullupEnable) // \arg enable pullup on PIO
|
|
450
|
{
|
|
451
|
// Connect or not Pullup
|
|
452
|
pPio->PIO_PPUER = pullupEnable;
|
|
453
|
}
|
|
454
|
|
|
455
|
static inline void AT91F_PIO_CfgPullupDis(
|
|
456
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
457
|
unsigned int pullupEnable) // \arg enable pullup on PIO
|
|
458
|
{
|
|
459
|
// Connect or not Pullup
|
|
460
|
pPio->PIO_PPUDR = pullupEnable;
|
|
461
|
}
|
|
462
|
|
|
463
|
//*----------------------------------------------------------------------------
|
|
464
|
//* \fn AT91F_PIO_CfgDirectDrive
|
|
465
|
//* \brief Enable direct drive on PIO
|
|
466
|
//*----------------------------------------------------------------------------
|
|
467
|
static inline void AT91F_PIO_CfgDirectDrive(
|
|
468
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
469
|
unsigned int directDrive) // \arg PIO to be configured with direct drive
|
|
470
|
|
|
471
|
{
|
|
472
|
// Configure the Direct Drive
|
|
473
|
pPio->PIO_OWDR = ~directDrive;
|
|
474
|
pPio->PIO_OWER = directDrive;
|
|
475
|
}
|
|
476
|
|
|
477
|
//*----------------------------------------------------------------------------
|
|
478
|
//* \fn AT91F_PIO_CfgInputFilter
|
|
479
|
//* \brief Enable input filter on input PIO
|
|
480
|
//*----------------------------------------------------------------------------
|
|
481
|
static inline void AT91F_PIO_CfgInputFilter(
|
|
482
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
483
|
unsigned int inputFilter) // \arg PIO to be configured with input filter
|
|
484
|
|
|
485
|
{
|
|
486
|
// Configure the Direct Drive
|
|
487
|
pPio->PIO_IFDR = ~inputFilter;
|
|
488
|
pPio->PIO_IFER = inputFilter;
|
|
489
|
}
|
|
490
|
|
|
491
|
//*----------------------------------------------------------------------------
|
|
492
|
//* \fn AT91F_PIO_GetInput
|
|
493
|
//* \brief Return PIO input value
|
|
494
|
//*----------------------------------------------------------------------------
|
|
495
|
static inline unsigned int AT91F_PIO_GetInput( // \return PIO input
|
|
496
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
497
|
{
|
|
498
|
return pPio->PIO_PDSR;
|
|
499
|
}
|
|
500
|
|
|
501
|
//*----------------------------------------------------------------------------
|
|
502
|
//* \fn AT91F_PIO_IsInputSet
|
|
503
|
//* \brief Test if PIO is input flag is active
|
|
504
|
//*----------------------------------------------------------------------------
|
|
505
|
static inline int AT91F_PIO_IsInputSet(
|
|
506
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
507
|
unsigned int flag) // \arg flag to be tested
|
|
508
|
{
|
|
509
|
return (AT91F_PIO_GetInput(pPio) & flag);
|
|
510
|
}
|
|
511
|
|
|
512
|
|
|
513
|
//*----------------------------------------------------------------------------
|
|
514
|
//* \fn AT91F_PIO_SetOutput
|
|
515
|
//* \brief Set to 1 output PIO
|
|
516
|
//*----------------------------------------------------------------------------
|
|
517
|
static inline void AT91F_PIO_SetOutput(
|
|
518
|
const AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
519
|
const unsigned int flag) // \arg output to be set
|
|
520
|
{
|
|
521
|
pPio->PIO_SODR = flag;
|
|
522
|
}
|
|
523
|
|
|
524
|
//*----------------------------------------------------------------------------
|
|
525
|
//* \fn AT91F_PIO_ClearOutput
|
|
526
|
//* \brief Set to 0 output PIO
|
|
527
|
//*----------------------------------------------------------------------------
|
|
528
|
static inline void AT91F_PIO_ClearOutput(
|
|
529
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
530
|
unsigned int flag) // \arg output to be cleared
|
|
531
|
{
|
|
532
|
pPio->PIO_CODR = flag;
|
|
533
|
}
|
|
534
|
|
|
535
|
//*----------------------------------------------------------------------------
|
|
536
|
//* \fn AT91F_PIO_ForceOutput
|
|
537
|
//* \brief Force output when Direct drive option is enabled
|
|
538
|
//*----------------------------------------------------------------------------
|
|
539
|
static inline void AT91F_PIO_ForceOutput(
|
|
540
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
541
|
unsigned int flag) // \arg output to be forced
|
|
542
|
{
|
|
543
|
pPio->PIO_ODSR = flag;
|
|
544
|
}
|
|
545
|
|
|
546
|
//*----------------------------------------------------------------------------
|
|
547
|
//* \fn AT91F_PIO_Enable
|
|
548
|
//* \brief Enable PIO
|
|
549
|
//*----------------------------------------------------------------------------
|
|
550
|
static inline void AT91F_PIO_Enable(
|
|
551
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
552
|
unsigned int flag) // \arg pio to be enabled
|
|
553
|
{
|
|
554
|
pPio->PIO_PER = flag;
|
|
555
|
}
|
|
556
|
|
|
557
|
//*----------------------------------------------------------------------------
|
|
558
|
//* \fn AT91F_PIO_Disable
|
|
559
|
//* \brief Disable PIO
|
|
560
|
//*----------------------------------------------------------------------------
|
|
561
|
static inline void AT91F_PIO_Disable(
|
|
562
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
563
|
unsigned int flag) // \arg pio to be disabled
|
|
564
|
{
|
|
565
|
pPio->PIO_PDR = flag;
|
|
566
|
}
|
|
567
|
|
|
568
|
//*----------------------------------------------------------------------------
|
|
569
|
//* \fn AT91F_PIO_GetStatus
|
|
570
|
//* \brief Return PIO Status
|
|
571
|
//*----------------------------------------------------------------------------
|
|
572
|
static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
|
|
573
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
574
|
{
|
|
575
|
return pPio->PIO_PSR;
|
|
576
|
}
|
|
577
|
|
|
578
|
//*----------------------------------------------------------------------------
|
|
579
|
//* \fn AT91F_PIO_IsSet
|
|
580
|
//* \brief Test if PIO is Set
|
|
581
|
//*----------------------------------------------------------------------------
|
|
582
|
static inline int AT91F_PIO_IsSet(
|
|
583
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
584
|
unsigned int flag) // \arg flag to be tested
|
|
585
|
{
|
|
586
|
return (AT91F_PIO_GetStatus(pPio) & flag);
|
|
587
|
}
|
|
588
|
|
|
589
|
//*----------------------------------------------------------------------------
|
|
590
|
//* \fn AT91F_PIO_OutputEnable
|
|
591
|
//* \brief Output Enable PIO
|
|
592
|
//*----------------------------------------------------------------------------
|
|
593
|
static inline void AT91F_PIO_OutputEnable(
|
|
594
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
595
|
unsigned int flag) // \arg pio output to be enabled
|
|
596
|
{
|
|
597
|
pPio->PIO_OER = flag;
|
|
598
|
}
|
|
599
|
|
|
600
|
//*----------------------------------------------------------------------------
|
|
601
|
//* \fn AT91F_PIO_OutputDisable
|
|
602
|
//* \brief Output Enable PIO
|
|
603
|
//*----------------------------------------------------------------------------
|
|
604
|
static inline void AT91F_PIO_OutputDisable(
|
|
605
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
606
|
unsigned int flag) // \arg pio output to be disabled
|
|
607
|
{
|
|
608
|
pPio->PIO_ODR = flag;
|
|
609
|
}
|
|
610
|
|
|
611
|
//*----------------------------------------------------------------------------
|
|
612
|
//* \fn AT91F_PIO_GetOutputStatus
|
|
613
|
//* \brief Return PIO Output Status
|
|
614
|
//*----------------------------------------------------------------------------
|
|
615
|
static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
|
|
616
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
617
|
{
|
|
618
|
return pPio->PIO_OSR;
|
|
619
|
}
|
|
620
|
|
|
621
|
//*----------------------------------------------------------------------------
|
|
622
|
//* \fn AT91F_PIO_IsOuputSet
|
|
623
|
//* \brief Test if PIO Output is Set
|
|
624
|
//*----------------------------------------------------------------------------
|
|
625
|
static inline int AT91F_PIO_IsOutputSet(
|
|
626
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
627
|
unsigned int flag) // \arg flag to be tested
|
|
628
|
{
|
|
629
|
return (AT91F_PIO_GetOutputStatus(pPio) & flag);
|
|
630
|
}
|
|
631
|
|
|
632
|
//*----------------------------------------------------------------------------
|
|
633
|
//* \fn AT91F_PIO_InputFilterEnable
|
|
634
|
//* \brief Input Filter Enable PIO
|
|
635
|
//*----------------------------------------------------------------------------
|
|
636
|
static inline void AT91F_PIO_InputFilterEnable(
|
|
637
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
638
|
unsigned int flag) // \arg pio input filter to be enabled
|
|
639
|
{
|
|
640
|
pPio->PIO_IFER = flag;
|
|
641
|
}
|
|
642
|
|
|
643
|
//*----------------------------------------------------------------------------
|
|
644
|
//* \fn AT91F_PIO_InputFilterDisable
|
|
645
|
//* \brief Input Filter Disable PIO
|
|
646
|
//*----------------------------------------------------------------------------
|
|
647
|
static inline void AT91F_PIO_InputFilterDisable(
|
|
648
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
649
|
unsigned int flag) // \arg pio input filter to be disabled
|
|
650
|
{
|
|
651
|
pPio->PIO_IFDR = flag;
|
|
652
|
}
|
|
653
|
|
|
654
|
//*----------------------------------------------------------------------------
|
|
655
|
//* \fn AT91F_PIO_GetInputFilterStatus
|
|
656
|
//* \brief Return PIO Input Filter Status
|
|
657
|
//*----------------------------------------------------------------------------
|
|
658
|
static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
|
|
659
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
660
|
{
|
|
661
|
return pPio->PIO_IFSR;
|
|
662
|
}
|
|
663
|
|
|
664
|
//*----------------------------------------------------------------------------
|
|
665
|
//* \fn AT91F_PIO_IsInputFilterSet
|
|
666
|
//* \brief Test if PIO Input filter is Set
|
|
667
|
//*----------------------------------------------------------------------------
|
|
668
|
static inline int AT91F_PIO_IsInputFilterSet(
|
|
669
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
670
|
unsigned int flag) // \arg flag to be tested
|
|
671
|
{
|
|
672
|
return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
|
|
673
|
}
|
|
674
|
|
|
675
|
//*----------------------------------------------------------------------------
|
|
676
|
//* \fn AT91F_PIO_GetOutputDataStatus
|
|
677
|
//* \brief Return PIO Output Data Status
|
|
678
|
//*----------------------------------------------------------------------------
|
|
679
|
static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
|
|
680
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
681
|
{
|
|
682
|
return pPio->PIO_ODSR;
|
|
683
|
}
|
|
684
|
|
|
685
|
//*----------------------------------------------------------------------------
|
|
686
|
//* \fn AT91F_PIO_InterruptEnable
|
|
687
|
//* \brief Enable PIO Interrupt
|
|
688
|
//*----------------------------------------------------------------------------
|
|
689
|
static inline void AT91F_PIO_InterruptEnable(
|
|
690
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
691
|
unsigned int flag) // \arg pio interrupt to be enabled
|
|
692
|
{
|
|
693
|
pPio->PIO_IER = flag;
|
|
694
|
}
|
|
695
|
|
|
696
|
//*----------------------------------------------------------------------------
|
|
697
|
//* \fn AT91F_PIO_InterruptDisable
|
|
698
|
//* \brief Disable PIO Interrupt
|
|
699
|
//*----------------------------------------------------------------------------
|
|
700
|
static inline void AT91F_PIO_InterruptDisable(
|
|
701
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
702
|
unsigned int flag) // \arg pio interrupt to be disabled
|
|
703
|
{
|
|
704
|
pPio->PIO_IDR = flag;
|
|
705
|
}
|
|
706
|
|
|
707
|
//*----------------------------------------------------------------------------
|
|
708
|
//* \fn AT91F_PIO_GetInterruptMaskStatus
|
|
709
|
//* \brief Return PIO Interrupt Mask Status
|
|
710
|
//*----------------------------------------------------------------------------
|
|
711
|
static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
|
|
712
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
713
|
{
|
|
714
|
return pPio->PIO_IMR;
|
|
715
|
}
|
|
716
|
|
|
717
|
//*----------------------------------------------------------------------------
|
|
718
|
//* \fn AT91F_PIO_GetInterruptStatus
|
|
719
|
//* \brief Return PIO Interrupt Status
|
|
720
|
//*----------------------------------------------------------------------------
|
|
721
|
static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
|
|
722
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
723
|
{
|
|
724
|
return pPio->PIO_ISR;
|
|
725
|
}
|
|
726
|
|
|
727
|
//*----------------------------------------------------------------------------
|
|
728
|
//* \fn AT91F_PIO_IsInterruptMasked
|
|
729
|
//* \brief Test if PIO Interrupt is Masked
|
|
730
|
//*----------------------------------------------------------------------------
|
|
731
|
static inline int AT91F_PIO_IsInterruptMasked(
|
|
732
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
733
|
unsigned int flag) // \arg flag to be tested
|
|
734
|
{
|
|
735
|
return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
|
|
736
|
}
|
|
737
|
|
|
738
|
//*----------------------------------------------------------------------------
|
|
739
|
//* \fn AT91F_PIO_IsInterruptSet
|
|
740
|
//* \brief Test if PIO Interrupt is Set
|
|
741
|
//*----------------------------------------------------------------------------
|
|
742
|
static inline int AT91F_PIO_IsInterruptSet(
|
|
743
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
744
|
unsigned int flag) // \arg flag to be tested
|
|
745
|
{
|
|
746
|
return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
|
|
747
|
}
|
|
748
|
|
|
749
|
//*----------------------------------------------------------------------------
|
|
750
|
//* \fn AT91F_PIO_MultiDriverEnable
|
|
751
|
//* \brief Multi Driver Enable PIO
|
|
752
|
//*----------------------------------------------------------------------------
|
|
753
|
static inline void AT91F_PIO_MultiDriverEnable(
|
|
754
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
755
|
unsigned int flag) // \arg pio to be enabled
|
|
756
|
{
|
|
757
|
pPio->PIO_MDER = flag;
|
|
758
|
}
|
|
759
|
|
|
760
|
//*----------------------------------------------------------------------------
|
|
761
|
//* \fn AT91F_PIO_MultiDriverDisable
|
|
762
|
//* \brief Multi Driver Disable PIO
|
|
763
|
//*----------------------------------------------------------------------------
|
|
764
|
static inline void AT91F_PIO_MultiDriverDisable(
|
|
765
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
766
|
unsigned int flag) // \arg pio to be disabled
|
|
767
|
{
|
|
768
|
pPio->PIO_MDDR = flag;
|
|
769
|
}
|
|
770
|
|
|
771
|
//*----------------------------------------------------------------------------
|
|
772
|
//* \fn AT91F_PIO_GetMultiDriverStatus
|
|
773
|
//* \brief Return PIO Multi Driver Status
|
|
774
|
//*----------------------------------------------------------------------------
|
|
775
|
static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
|
|
776
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
777
|
{
|
|
778
|
return pPio->PIO_MDSR;
|
|
779
|
}
|
|
780
|
|
|
781
|
//*----------------------------------------------------------------------------
|
|
782
|
//* \fn AT91F_PIO_IsMultiDriverSet
|
|
783
|
//* \brief Test if PIO MultiDriver is Set
|
|
784
|
//*----------------------------------------------------------------------------
|
|
785
|
static inline int AT91F_PIO_IsMultiDriverSet(
|
|
786
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
787
|
unsigned int flag) // \arg flag to be tested
|
|
788
|
{
|
|
789
|
return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
|
|
790
|
}
|
|
791
|
|
|
792
|
//*----------------------------------------------------------------------------
|
|
793
|
//* \fn AT91F_PIO_A_RegisterSelection
|
|
794
|
//* \brief PIO A Register Selection
|
|
795
|
//*----------------------------------------------------------------------------
|
|
796
|
static inline void AT91F_PIO_A_RegisterSelection(
|
|
797
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
798
|
unsigned int flag) // \arg pio A register selection
|
|
799
|
{
|
|
800
|
pPio->PIO_ASR = flag;
|
|
801
|
}
|
|
802
|
|
|
803
|
//*----------------------------------------------------------------------------
|
|
804
|
//* \fn AT91F_PIO_B_RegisterSelection
|
|
805
|
//* \brief PIO B Register Selection
|
|
806
|
//*----------------------------------------------------------------------------
|
|
807
|
static inline void AT91F_PIO_B_RegisterSelection(
|
|
808
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
809
|
unsigned int flag) // \arg pio B register selection
|
|
810
|
{
|
|
811
|
pPio->PIO_BSR = flag;
|
|
812
|
}
|
|
813
|
|
|
814
|
//*----------------------------------------------------------------------------
|
|
815
|
//* \fn AT91F_PIO_Get_AB_RegisterStatus
|
|
816
|
//* \brief Return PIO Interrupt Status
|
|
817
|
//*----------------------------------------------------------------------------
|
|
818
|
static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
|
|
819
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
820
|
{
|
|
821
|
return pPio->PIO_ABSR;
|
|
822
|
}
|
|
823
|
|
|
824
|
//*----------------------------------------------------------------------------
|
|
825
|
//* \fn AT91F_PIO_IsAB_RegisterSet
|
|
826
|
//* \brief Test if PIO AB Register is Set
|
|
827
|
//*----------------------------------------------------------------------------
|
|
828
|
static inline int AT91F_PIO_IsAB_RegisterSet(
|
|
829
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
830
|
unsigned int flag) // \arg flag to be tested
|
|
831
|
{
|
|
832
|
return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
|
|
833
|
}
|
|
834
|
|
|
835
|
//*----------------------------------------------------------------------------
|
|
836
|
//* \fn AT91F_PIO_OutputWriteEnable
|
|
837
|
//* \brief Output Write Enable PIO
|
|
838
|
//*----------------------------------------------------------------------------
|
|
839
|
static inline void AT91F_PIO_OutputWriteEnable(
|
|
840
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
841
|
unsigned int flag) // \arg pio output write to be enabled
|
|
842
|
{
|
|
843
|
pPio->PIO_OWER = flag;
|
|
844
|
}
|
|
845
|
|
|
846
|
//*----------------------------------------------------------------------------
|
|
847
|
//* \fn AT91F_PIO_OutputWriteDisable
|
|
848
|
//* \brief Output Write Disable PIO
|
|
849
|
//*----------------------------------------------------------------------------
|
|
850
|
static inline void AT91F_PIO_OutputWriteDisable(
|
|
851
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
852
|
unsigned int flag) // \arg pio output write to be disabled
|
|
853
|
{
|
|
854
|
pPio->PIO_OWDR = flag;
|
|
855
|
}
|
|
856
|
|
|
857
|
//*----------------------------------------------------------------------------
|
|
858
|
//* \fn AT91F_PIO_GetOutputWriteStatus
|
|
859
|
//* \brief Return PIO Output Write Status
|
|
860
|
//*----------------------------------------------------------------------------
|
|
861
|
static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
|
|
862
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
863
|
{
|
|
864
|
return pPio->PIO_OWSR;
|
|
865
|
}
|
|
866
|
|
|
867
|
//*----------------------------------------------------------------------------
|
|
868
|
//* \fn AT91F_PIO_IsOutputWriteSet
|
|
869
|
//* \brief Test if PIO OutputWrite is Set
|
|
870
|
//*----------------------------------------------------------------------------
|
|
871
|
static inline int AT91F_PIO_IsOutputWriteSet(
|
|
872
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
873
|
unsigned int flag) // \arg flag to be tested
|
|
874
|
{
|
|
875
|
return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
|
|
876
|
}
|
|
877
|
|
|
878
|
//*----------------------------------------------------------------------------
|
|
879
|
//* \fn AT91F_PIO_GetCfgPullup
|
|
880
|
//* \brief Return PIO Configuration Pullup
|
|
881
|
//*----------------------------------------------------------------------------
|
|
882
|
static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
|
|
883
|
AT91PS_PIO pPio) // \arg pointer to a PIO controller
|
|
884
|
{
|
|
885
|
return pPio->PIO_PPUSR;
|
|
886
|
}
|
|
887
|
|
|
888
|
//*----------------------------------------------------------------------------
|
|
889
|
//* \fn AT91F_PIO_IsOutputDataStatusSet
|
|
890
|
//* \brief Test if PIO Output Data Status is Set
|
|
891
|
//*----------------------------------------------------------------------------
|
|
892
|
static inline int AT91F_PIO_IsOutputDataStatusSet(
|
|
893
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
894
|
unsigned int flag) // \arg flag to be tested
|
|
895
|
{
|
|
896
|
return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
|
|
897
|
}
|
|
898
|
|
|
899
|
//*----------------------------------------------------------------------------
|
|
900
|
//* \fn AT91F_PIO_IsCfgPullupStatusSet
|
|
901
|
//* \brief Test if PIO Configuration Pullup Status is Set
|
|
902
|
//*----------------------------------------------------------------------------
|
|
903
|
static inline int AT91F_PIO_IsCfgPullupStatusSet(
|
|
904
|
AT91PS_PIO pPio, // \arg pointer to a PIO controller
|
|
905
|
unsigned int flag) // \arg flag to be tested
|
|
906
|
{
|
|
907
|
return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
|
|
908
|
}
|
|
909
|
|
|
910
|
/* *****************************************************************************
|
|
911
|
SOFTWARE API FOR PMC
|
|
912
|
***************************************************************************** */
|
|
913
|
//*----------------------------------------------------------------------------
|
|
914
|
//* \fn AT91F_PMC_CfgSysClkEnableReg
|
|
915
|
//* \brief Configure the System Clock Enable Register of the PMC controller
|
|
916
|
//*----------------------------------------------------------------------------
|
|
917
|
static inline void AT91F_PMC_CfgSysClkEnableReg (
|
|
918
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
919
|
unsigned int mode)
|
|
920
|
{
|
|
921
|
//* Write to the SCER register
|
|
922
|
pPMC->PMC_SCER = mode;
|
|
923
|
}
|
|
924
|
|
|
925
|
//*----------------------------------------------------------------------------
|
|
926
|
//* \fn AT91F_PMC_CfgSysClkDisableReg
|
|
927
|
//* \brief Configure the System Clock Disable Register of the PMC controller
|
|
928
|
//*----------------------------------------------------------------------------
|
|
929
|
static inline void AT91F_PMC_CfgSysClkDisableReg (
|
|
930
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
931
|
unsigned int mode)
|
|
932
|
{
|
|
933
|
//* Write to the SCDR register
|
|
934
|
pPMC->PMC_SCDR = mode;
|
|
935
|
}
|
|
936
|
|
|
937
|
//*----------------------------------------------------------------------------
|
|
938
|
//* \fn AT91F_PMC_GetSysClkStatusReg
|
|
939
|
//* \brief Return the System Clock Status Register of the PMC controller
|
|
940
|
//*----------------------------------------------------------------------------
|
|
941
|
static inline unsigned int AT91F_PMC_GetSysClkStatusReg (
|
|
942
|
AT91PS_PMC pPMC // pointer to a CAN controller
|
|
943
|
)
|
|
944
|
{
|
|
945
|
return pPMC->PMC_SCSR;
|
|
946
|
}
|
|
947
|
|
|
948
|
//*----------------------------------------------------------------------------
|
|
949
|
//* \fn AT91F_PMC_EnablePeriphClock
|
|
950
|
//* \brief Enable peripheral clock
|
|
951
|
//*----------------------------------------------------------------------------
|
|
952
|
static inline void AT91F_PMC_EnablePeriphClock (
|
|
953
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
954
|
unsigned int periphIds) // \arg IDs of peripherals to enable
|
|
955
|
{
|
|
956
|
pPMC->PMC_PCER = periphIds;
|
|
957
|
}
|
|
958
|
|
|
959
|
//*----------------------------------------------------------------------------
|
|
960
|
//* \fn AT91F_PMC_DisablePeriphClock
|
|
961
|
//* \brief Disable peripheral clock
|
|
962
|
//*----------------------------------------------------------------------------
|
|
963
|
static inline void AT91F_PMC_DisablePeriphClock (
|
|
964
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
965
|
unsigned int periphIds) // \arg IDs of peripherals to enable
|
|
966
|
{
|
|
967
|
pPMC->PMC_PCDR = periphIds;
|
|
968
|
}
|
|
969
|
|
|
970
|
//*----------------------------------------------------------------------------
|
|
971
|
//* \fn AT91F_PMC_GetPeriphClock
|
|
972
|
//* \brief Get peripheral clock status
|
|
973
|
//*----------------------------------------------------------------------------
|
|
974
|
static inline unsigned int AT91F_PMC_GetPeriphClock (
|
|
975
|
AT91PS_PMC pPMC) // \arg pointer to PMC controller
|
|
976
|
{
|
|
977
|
return pPMC->PMC_PCSR;
|
|
978
|
}
|
|
979
|
|
|
980
|
//*----------------------------------------------------------------------------
|
|
981
|
//* \fn AT91F_CKGR_CfgMainOscillatorReg
|
|
982
|
//* \brief Cfg the main oscillator
|
|
983
|
//*----------------------------------------------------------------------------
|
|
984
|
static inline void AT91F_CKGR_CfgMainOscillatorReg (
|
|
985
|
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
|
|
986
|
unsigned int mode)
|
|
987
|
{
|
|
988
|
pCKGR->CKGR_MOR = mode;
|
|
989
|
}
|
|
990
|
|
|
991
|
//*----------------------------------------------------------------------------
|
|
992
|
//* \fn AT91F_CKGR_GetMainOscillatorReg
|
|
993
|
//* \brief Cfg the main oscillator
|
|
994
|
//*----------------------------------------------------------------------------
|
|
995
|
static inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
|
|
996
|
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
|
|
997
|
{
|
|
998
|
return pCKGR->CKGR_MOR;
|
|
999
|
}
|
|
1000
|
|
|
1001
|
//*----------------------------------------------------------------------------
|
|
1002
|
//* \fn AT91F_CKGR_EnableMainOscillator
|
|
1003
|
//* \brief Enable the main oscillator
|
|
1004
|
//*----------------------------------------------------------------------------
|
|
1005
|
static inline void AT91F_CKGR_EnableMainOscillator(
|
|
1006
|
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
|
|
1007
|
{
|
|
1008
|
pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
|
|
1009
|
}
|
|
1010
|
|
|
1011
|
//*----------------------------------------------------------------------------
|
|
1012
|
//* \fn AT91F_CKGR_DisableMainOscillator
|
|
1013
|
//* \brief Disable the main oscillator
|
|
1014
|
//*----------------------------------------------------------------------------
|
|
1015
|
static inline void AT91F_CKGR_DisableMainOscillator (
|
|
1016
|
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
|
|
1017
|
{
|
|
1018
|
pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
|
|
1019
|
}
|
|
1020
|
|
|
1021
|
//*----------------------------------------------------------------------------
|
|
1022
|
//* \fn AT91F_CKGR_CfgMainOscStartUpTime
|
|
1023
|
//* \brief Cfg MOR Register according to the main osc startup time
|
|
1024
|
//*----------------------------------------------------------------------------
|
|
1025
|
static inline void AT91F_CKGR_CfgMainOscStartUpTime (
|
|
1026
|
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
|
|
1027
|
unsigned int startup_time, // \arg main osc startup time in microsecond (us)
|
|
1028
|
unsigned int slowClock) // \arg slowClock in Hz
|
|
1029
|
{
|
|
1030
|
pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
|
|
1031
|
pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
|
|
1032
|
}
|
|
1033
|
|
|
1034
|
//*----------------------------------------------------------------------------
|
|
1035
|
//* \fn AT91F_CKGR_GetMainClockFreqReg
|
|
1036
|
//* \brief Cfg the main oscillator
|
|
1037
|
//*----------------------------------------------------------------------------
|
|
1038
|
static inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
|
|
1039
|
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
|
|
1040
|
{
|
|
1041
|
return pCKGR->CKGR_MCFR;
|
|
1042
|
}
|
|
1043
|
|
|
1044
|
//*----------------------------------------------------------------------------
|
|
1045
|
//* \fn AT91F_CKGR_GetMainClock
|
|
1046
|
//* \brief Return Main clock in Hz
|
|
1047
|
//*----------------------------------------------------------------------------
|
|
1048
|
static inline unsigned int AT91F_CKGR_GetMainClock (
|
|
1049
|
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
|
|
1050
|
unsigned int slowClock) // \arg slowClock in Hz
|
|
1051
|
{
|
|
1052
|
return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
|
|
1053
|
}
|
|
1054
|
|
|
1055
|
//*----------------------------------------------------------------------------
|
|
1056
|
//* \fn AT91F_PMC_CfgMCKReg
|
|
1057
|
//* \brief Cfg Master Clock Register
|
|
1058
|
//*----------------------------------------------------------------------------
|
|
1059
|
static inline void AT91F_PMC_CfgMCKReg (
|
|
1060
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
1061
|
unsigned int mode)
|
|
1062
|
{
|
|
1063
|
pPMC->PMC_MCKR = mode;
|
|
1064
|
}
|
|
1065
|
|
|
1066
|
//*----------------------------------------------------------------------------
|
|
1067
|
//* \fn AT91F_PMC_GetMCKReg
|
|
1068
|
//* \brief Return Master Clock Register
|
|
1069
|
//*----------------------------------------------------------------------------
|
|
1070
|
static inline unsigned int AT91F_PMC_GetMCKReg(
|
|
1071
|
AT91PS_PMC pPMC) // \arg pointer to PMC controller
|
|
1072
|
{
|
|
1073
|
return pPMC->PMC_MCKR;
|
|
1074
|
}
|
|
1075
|
|
|
1076
|
//*------------------------------------------------------------------------------
|
|
1077
|
//* \fn AT91F_PMC_GetMasterClock
|
|
1078
|
//* \brief Return master clock in Hz which correponds to processor clock for ARM7
|
|
1079
|
//*------------------------------------------------------------------------------
|
|
1080
|
extern unsigned int AT91F_PMC_GetMasterClock (
|
|
1081
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
1082
|
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
|
|
1083
|
unsigned int slowClock); // \arg slowClock in Hz
|
|
1084
|
|
|
1085
|
//*----------------------------------------------------------------------------
|
|
1086
|
//* \fn AT91F_PMC_EnablePCK
|
|
1087
|
//* \brief Enable peripheral clock
|
|
1088
|
//*----------------------------------------------------------------------------
|
|
1089
|
static inline void AT91F_PMC_EnablePCK (
|
|
1090
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
1091
|
unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
|
|
1092
|
unsigned int mode)
|
|
1093
|
{
|
|
1094
|
pPMC->PMC_PCKR[pck] = mode;
|
|
1095
|
pPMC->PMC_SCER = (1 << pck) << 8;
|
|
1096
|
}
|
|
1097
|
|
|
1098
|
//*----------------------------------------------------------------------------
|
|
1099
|
//* \fn AT91F_PMC_DisablePCK
|
|
1100
|
//* \brief Enable peripheral clock
|
|
1101
|
//*----------------------------------------------------------------------------
|
|
1102
|
static inline void AT91F_PMC_DisablePCK (
|
|
1103
|
AT91PS_PMC pPMC, // \arg pointer to PMC controller
|
|
1104
|
unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
|
|
1105
|
{
|
|
1106
|
pPMC->PMC_SCDR = (1 << pck) << 8;
|
|
1107
|
}
|
|
1108
|
|
|
1109
|
//*----------------------------------------------------------------------------
|
|
1110
|
//* \fn AT91F_PMC_EnableIt
|
|
1111
|
//* \brief Enable PMC interrupt
|
|
1112
|
//*----------------------------------------------------------------------------
|
|
1113
|
static inline void AT91F_PMC_EnableIt (
|
|
1114
|
AT91PS_PMC pPMC, // pointer to a PMC controller
|
|
1115
|
unsigned int flag) // IT to be enabled
|
|
1116
|
{
|
|
1117
|
//* Write to the IER register
|
|
1118
|
pPMC->PMC_IER = flag;
|
|
1119
|
}
|
|
1120
|
|
|
1121
|
//*----------------------------------------------------------------------------
|
|
1122
|
//* \fn AT91F_PMC_DisableIt
|
|
1123
|
//* \brief Disable PMC interrupt
|
|
1124
|
//*----------------------------------------------------------------------------
|
|
1125
|
static inline void AT91F_PMC_DisableIt (
|
|
1126
|
AT91PS_PMC pPMC, // pointer to a PMC controller
|
|
1127
|
unsigned int flag) // IT to be disabled
|
|
1128
|
{
|
|
1129
|
//* Write to the IDR register
|
|
1130
|
pPMC->PMC_IDR = flag;
|
|
1131
|
}
|
|
1132
|
|
|
1133
|
//*----------------------------------------------------------------------------
|
|
1134
|
//* \fn AT91F_PMC_GetStatus
|
|
1135
|
//* \brief Return PMC Interrupt Status
|
|
1136
|
//*----------------------------------------------------------------------------
|
|
1137
|
static inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
|
|
1138
|
AT91PS_PMC pPMC) // pointer to a PMC controller
|
|
1139
|
{
|
|
1140
|
return pPMC->PMC_SR;
|
|
1141
|
}
|
|
1142
|
|
|
1143
|
//*----------------------------------------------------------------------------
|
|
1144
|
//* \fn AT91F_PMC_GetInterruptMaskStatus
|
|
1145
|
//* \brief Return PMC Interrupt Mask Status
|
|
1146
|
//*----------------------------------------------------------------------------
|
|
1147
|
static inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
|
|
1148
|
AT91PS_PMC pPMC) // pointer to a PMC controller
|
|
1149
|
{
|
|
1150
|
return pPMC->PMC_IMR;
|
|
1151
|
}
|
|
1152
|
|
|
1153
|
//*----------------------------------------------------------------------------
|
|
1154
|
//* \fn AT91F_PMC_IsInterruptMasked
|
|
1155
|
//* \brief Test if PMC Interrupt is Masked
|
|
1156
|
//*----------------------------------------------------------------------------
|
|
1157
|
static inline unsigned int AT91F_PMC_IsInterruptMasked(
|
|
1158
|
AT91PS_PMC pPMC, // \arg pointer to a PMC controller
|
|
1159
|
unsigned int flag) // \arg flag to be tested
|
|
1160
|
{
|
|
1161
|
return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
|
|
1162
|
}
|
|
1163
|
|
|
1164
|
//*----------------------------------------------------------------------------
|
|
1165
|
//* \fn AT91F_PMC_IsStatusSet
|
|
1166
|
//* \brief Test if PMC Status is Set
|
|
1167
|
//*----------------------------------------------------------------------------
|
|
1168
|
static inline unsigned int AT91F_PMC_IsStatusSet(
|
|
1169
|
AT91PS_PMC pPMC, // \arg pointer to a PMC controller
|
|
1170
|
unsigned int flag) // \arg flag to be tested
|
|
1171
|
{
|
|
1172
|
return (AT91F_PMC_GetStatus(pPMC) & flag);
|
|
1173
|
}
|
|
1174
|
|
|
1175
|
// ----------------------------------------------------------------------------
|
|
1176
|
// \fn AT91F_CKGR_CfgPLLReg
|
|
1177
|
// \brief Cfg the PLL Register
|
|
1178
|
// ----------------------------------------------------------------------------
|
|
1179
|
static inline void AT91F_CKGR_CfgPLLReg (
|
|
1180
|
AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
|
|
1181
|
unsigned int mode)
|
|
1182
|
{
|
|
1183
|
pCKGR->CKGR_PLLR = mode;
|
|
1184
|
}
|
|
1185
|
|
|
1186
|
// ----------------------------------------------------------------------------
|
|
1187
|
// \fn AT91F_CKGR_GetPLLReg
|
|
1188
|
// \brief Get the PLL Register
|
|
1189
|
// ----------------------------------------------------------------------------
|
|
1190
|
static inline unsigned int AT91F_CKGR_GetPLLReg (
|
|
1191
|
AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
|
|
1192
|
{
|
|
1193
|
return pCKGR->CKGR_PLLR;
|
|
1194
|
}
|
|
1195
|
|
|
1196
|
|
|
1197
|
|
|
1198
|
/* *****************************************************************************
|
|
1199
|
SOFTWARE API FOR RSTC
|
|
1200
|
***************************************************************************** */
|
|
1201
|
//*----------------------------------------------------------------------------
|
|
1202
|
//* \fn AT91F_RSTSoftReset
|
|
1203
|
//* \brief Start Software Reset
|
|
1204
|
//*----------------------------------------------------------------------------
|
|
1205
|
static inline void AT91F_RSTSoftReset(
|
|
1206
|
AT91PS_RSTC pRSTC,
|
|
1207
|
unsigned int reset)
|
|
1208
|
{
|
|
1209
|
pRSTC->RSTC_RCR = (0xA5000000 | reset);
|
|
1210
|
}
|
|
1211
|
|
|
1212
|
//*----------------------------------------------------------------------------
|
|
1213
|
//* \fn AT91F_RSTSetMode
|
|
1214
|
//* \brief Set Reset Mode
|
|
1215
|
//*----------------------------------------------------------------------------
|
|
1216
|
static inline void AT91F_RSTSetMode(
|
|
1217
|
AT91PS_RSTC pRSTC,
|
|
1218
|
unsigned int mode)
|
|
1219
|
{
|
|
1220
|
pRSTC->RSTC_RMR = (0xA5000000 | mode);
|
|
1221
|
}
|
|
1222
|
|
|
1223
|
//*----------------------------------------------------------------------------
|
|
1224
|
//* \fn AT91F_RSTGetMode
|
|
1225
|
//* \brief Get Reset Mode
|
|
1226
|
//*----------------------------------------------------------------------------
|
|
1227
|
static inline unsigned int AT91F_RSTGetMode(
|
|
1228
|
AT91PS_RSTC pRSTC)
|
|
1229
|
{
|
|
1230
|
return (pRSTC->RSTC_RMR);
|
|
1231
|
}
|
|
1232
|
|
|
1233
|
//*----------------------------------------------------------------------------
|
|
1234
|
//* \fn AT91F_RSTGetStatus
|
|
1235
|
//* \brief Get Reset Status
|
|
1236
|
//*----------------------------------------------------------------------------
|
|
1237
|
static inline unsigned int AT91F_RSTGetStatus(
|
|
1238
|
AT91PS_RSTC pRSTC)
|
|
1239
|
{
|
|
1240
|
return (pRSTC->RSTC_RSR);
|
|
1241
|
}
|
|
1242
|
|
|
1243
|
//*----------------------------------------------------------------------------
|
|
1244
|
//* \fn AT91F_RSTIsSoftRstActive
|
|
1245
|
//* \brief Return !=0 if software reset is still not completed
|
|
1246
|
//*----------------------------------------------------------------------------
|
|
1247
|
static inline unsigned int AT91F_RSTIsSoftRstActive(
|
|
1248
|
AT91PS_RSTC pRSTC)
|
|
1249
|
{
|
|
1250
|
return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
|
|
1251
|
}
|
|
1252
|
/* *****************************************************************************
|
|
1253
|
SOFTWARE API FOR RTTC
|
|
1254
|
***************************************************************************** */
|
|
1255
|
//*--------------------------------------------------------------------------------------
|
|
1256
|
//* \fn AT91F_SetRTT_TimeBase()
|
|
1257
|
//* \brief Set the RTT prescaler according to the TimeBase in ms
|
|
1258
|
//*--------------------------------------------------------------------------------------
|
|
1259
|
static inline unsigned int AT91F_RTTSetTimeBase(
|
|
1260
|
AT91PS_RTTC pRTTC,
|
|
1261
|
unsigned int ms)
|
|
1262
|
{
|
|
1263
|
if (ms > 2000)
|
|
1264
|
return 1; // AT91C_TIME_OUT_OF_RANGE
|
|
1265
|
pRTTC->RTTC_RTMR &= ~0xFFFF;
|
|
1266
|
pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
|
|
1267
|
return 0;
|
|
1268
|
}
|
|
1269
|
|
|
1270
|
//*--------------------------------------------------------------------------------------
|
|
1271
|
//* \fn AT91F_RTTSetPrescaler()
|
|
1272
|
//* \brief Set the new prescaler value
|
|
1273
|
//*--------------------------------------------------------------------------------------
|
|
1274
|
static inline unsigned int AT91F_RTTSetPrescaler(
|
|
1275
|
AT91PS_RTTC pRTTC,
|
|
1276
|
unsigned int rtpres)
|
|
1277
|
{
|
|
1278
|
pRTTC->RTTC_RTMR &= ~0xFFFF;
|
|
1279
|
pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
|
|
1280
|
return (pRTTC->RTTC_RTMR);
|
|
1281
|
}
|
|
1282
|
|
|
1283
|
//*--------------------------------------------------------------------------------------
|
|
1284
|
//* \fn AT91F_RTTRestart()
|
|
1285
|
//* \brief Restart the RTT prescaler
|
|
1286
|
//*--------------------------------------------------------------------------------------
|
|
1287
|
static inline void AT91F_RTTRestart(
|
|
1288
|
AT91PS_RTTC pRTTC)
|
|
1289
|
{
|
|
1290
|
pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
|
|
1291
|
}
|
|
1292
|
|
|
1293
|
|
|
1294
|
//*--------------------------------------------------------------------------------------
|
|
1295
|
//* \fn AT91F_RTT_SetAlarmINT()
|
|
1296
|
//* \brief Enable RTT Alarm Interrupt
|
|
1297
|
//*--------------------------------------------------------------------------------------
|
|
1298
|
static inline void AT91F_RTTSetAlarmINT(
|
|
1299
|
AT91PS_RTTC pRTTC)
|
|
1300
|
{
|
|
1301
|
pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
|
|
1302
|
}
|
|
1303
|
|
|
1304
|
//*--------------------------------------------------------------------------------------
|
|
1305
|
//* \fn AT91F_RTT_ClearAlarmINT()
|
|
1306
|
//* \brief Disable RTT Alarm Interrupt
|
|
1307
|
//*--------------------------------------------------------------------------------------
|
|
1308
|
static inline void AT91F_RTTClearAlarmINT(
|
|
1309
|
AT91PS_RTTC pRTTC)
|
|
1310
|
{
|
|
1311
|
pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
|
|
1312
|
}
|
|
1313
|
|
|
1314
|
//*--------------------------------------------------------------------------------------
|
|
1315
|
//* \fn AT91F_RTT_SetRttIncINT()
|
|
1316
|
//* \brief Enable RTT INC Interrupt
|
|
1317
|
//*--------------------------------------------------------------------------------------
|
|
1318
|
static inline void AT91F_RTTSetRttIncINT(
|
|
1319
|
AT91PS_RTTC pRTTC)
|
|
1320
|
{
|
|
1321
|
pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
|
|
1322
|
}
|
|
1323
|
|
|
1324
|
//*--------------------------------------------------------------------------------------
|
|
1325
|
//* \fn AT91F_RTT_ClearRttIncINT()
|
|
1326
|
//* \brief Disable RTT INC Interrupt
|
|
1327
|
//*--------------------------------------------------------------------------------------
|
|
1328
|
static inline void AT91F_RTTClearRttIncINT(
|
|
1329
|
AT91PS_RTTC pRTTC)
|
|
1330
|
{
|
|
1331
|
pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
|
|
1332
|
}
|
|
1333
|
|
|
1334
|
//*--------------------------------------------------------------------------------------
|
|
1335
|
//* \fn AT91F_RTT_SetAlarmValue()
|
|
1336
|
//* \brief Set RTT Alarm Value
|
|
1337
|
//*--------------------------------------------------------------------------------------
|
|
1338
|
static inline void AT91F_RTTSetAlarmValue(
|
|
1339
|
AT91PS_RTTC pRTTC, unsigned int _alarm)
|
|
1340
|
{
|
|
1341
|
pRTTC->RTTC_RTAR = _alarm;
|
|
1342
|
}
|
|
1343
|
|
|
1344
|
//*--------------------------------------------------------------------------------------
|
|
1345
|
//* \fn AT91F_RTT_GetAlarmValue()
|
|
1346
|
//* \brief Get RTT Alarm Value
|
|
1347
|
//*--------------------------------------------------------------------------------------
|
|
1348
|
static inline unsigned int AT91F_RTTGetAlarmValue(
|
|
1349
|
AT91PS_RTTC pRTTC)
|
|
1350
|
{
|
|
1351
|
return(pRTTC->RTTC_RTAR);
|
|
1352
|
}
|
|
1353
|
|
|
1354
|
//*--------------------------------------------------------------------------------------
|
|
1355
|
//* \fn AT91F_RTTGetStatus()
|
|
1356
|
//* \brief Read the RTT status
|
|
1357
|
//*--------------------------------------------------------------------------------------
|
|
1358
|
static inline unsigned int AT91F_RTTGetStatus(
|
|
1359
|
AT91PS_RTTC pRTTC)
|
|
1360
|
{
|
|
1361
|
return(pRTTC->RTTC_RTSR);
|
|
1362
|
}
|
|
1363
|
|
|
1364
|
//*--------------------------------------------------------------------------------------
|
|
1365
|
//* \fn AT91F_RTT_ReadValue()
|
|
1366
|
//* \brief Read the RTT value
|
|
1367
|
//*--------------------------------------------------------------------------------------
|
|
1368
|
extern unsigned int AT91F_RTTReadValue(AT91PS_RTTC pRTTC);
|
|
1369
|
|
|
1370
|
/* *****************************************************************************
|
|
1371
|
SOFTWARE API FOR PITC
|
|
1372
|
***************************************************************************** */
|
|
1373
|
//*----------------------------------------------------------------------------
|
|
1374
|
//* \fn AT91F_PITInit
|
|
1375
|
//* \brief System timer init : period in ?second, system clock freq in MHz
|
|
1376
|
//*----------------------------------------------------------------------------
|
|
1377
|
static inline void AT91F_PITInit(
|
|
1378
|
AT91PS_PITC pPITC,
|
|
1379
|
unsigned int period,
|
|
1380
|
unsigned int pit_frequency)
|
|
1381
|
{
|
|
1382
|
pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
|
|
1383
|
pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
|
|
1384
|
}
|
|
1385
|
|
|
1386
|
//*----------------------------------------------------------------------------
|
|
1387
|
//* \fn AT91F_PITSetPIV
|
|
1388
|
//* \brief Set the PIT Periodic Interval Value
|
|
1389
|
//*----------------------------------------------------------------------------
|
|
1390
|
static inline void AT91F_PITSetPIV(
|
|
1391
|
AT91PS_PITC pPITC,
|
|
1392
|
unsigned int piv)
|
|
1393
|
{
|
|
1394
|
pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
|
|
1395
|
}
|
|
1396
|
|
|
1397
|
//*----------------------------------------------------------------------------
|
|
1398
|
//* \fn AT91F_PITEnableInt
|
|
1399
|
//* \brief Enable PIT periodic interrupt
|
|
1400
|
//*----------------------------------------------------------------------------
|
|
1401
|
static inline void AT91F_PITEnableInt(
|
|
1402
|
AT91PS_PITC pPITC)
|
|
1403
|
{
|
|
1404
|
pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
|
|
1405
|
}
|
|
1406
|
|
|
1407
|
//*----------------------------------------------------------------------------
|
|
1408
|
//* \fn AT91F_PITDisableInt
|
|
1409
|
//* \brief Disable PIT periodic interrupt
|
|
1410
|
//*----------------------------------------------------------------------------
|
|
1411
|
static inline void AT91F_PITDisableInt(
|
|
1412
|
AT91PS_PITC pPITC)
|
|
1413
|
{
|
|
1414
|
pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
|
|
1415
|
}
|
|
1416
|
|
|
1417
|
//*----------------------------------------------------------------------------
|
|
1418
|
//* \fn AT91F_PITGetMode
|
|
1419
|
//* \brief Read PIT mode register
|
|
1420
|
//*----------------------------------------------------------------------------
|
|
1421
|
static inline unsigned int AT91F_PITGetMode(
|
|
1422
|
AT91PS_PITC pPITC)
|
|
1423
|
{
|
|
1424
|
return(pPITC->PITC_PIMR);
|
|
1425
|
}
|
|
1426
|
|
|
1427
|
//*----------------------------------------------------------------------------
|
|
1428
|
//* \fn AT91F_PITGetStatus
|
|
1429
|
//* \brief Read PIT status register
|
|
1430
|
//*----------------------------------------------------------------------------
|
|
1431
|
static inline unsigned int AT91F_PITGetStatus(
|
|
1432
|
AT91PS_PITC pPITC)
|
|
1433
|
{
|
|
1434
|
return(pPITC->PITC_PISR);
|
|
1435
|
}
|
|
1436
|
|
|
1437
|
//*----------------------------------------------------------------------------
|
|
1438
|
//* \fn AT91F_PITGetPIIR
|
|
1439
|
//* \brief Read PIT CPIV and PICNT without ressetting the counters
|
|
1440
|
//*----------------------------------------------------------------------------
|
|
1441
|
static inline unsigned int AT91F_PITGetPIIR(
|
|
1442
|
AT91PS_PITC pPITC)
|
|
1443
|
{
|
|
1444
|
return(pPITC->PITC_PIIR);
|
|
1445
|
}
|
|
1446
|
|
|
1447
|
//*----------------------------------------------------------------------------
|
|
1448
|
//* \fn AT91F_PITGetPIVR
|
|
1449
|
//* \brief Read System timer CPIV and PICNT without ressetting the counters
|
|
1450
|
//*----------------------------------------------------------------------------
|
|
1451
|
static inline unsigned int AT91F_PITGetPIVR(
|
|
1452
|
AT91PS_PITC pPITC)
|
|
1453
|
{
|
|
1454
|
return(pPITC->PITC_PIVR);
|
|
1455
|
}
|
|
1456
|
/* *****************************************************************************
|
|
1457
|
SOFTWARE API FOR WDTC
|
|
1458
|
***************************************************************************** */
|
|
1459
|
//*----------------------------------------------------------------------------
|
|
1460
|
//* \fn AT91F_WDTSetMode
|
|
1461
|
//* \brief Set Watchdog Mode Register
|
|
1462
|
//*----------------------------------------------------------------------------
|
|
1463
|
static inline void AT91F_WDTSetMode(
|
|
1464
|
AT91PS_WDTC pWDTC,
|
|
1465
|
unsigned int Mode)
|
|
1466
|
{
|
|
1467
|
pWDTC->WDTC_WDMR = Mode;
|
|
1468
|
}
|
|
1469
|
|
|
1470
|
//*----------------------------------------------------------------------------
|
|
1471
|
//* \fn AT91F_WDTRestart
|
|
1472
|
//* \brief Restart Watchdog
|
|
1473
|
//*----------------------------------------------------------------------------
|
|
1474
|
static inline void AT91F_WDTRestart(
|
|
1475
|
AT91PS_WDTC pWDTC)
|
|
1476
|
{
|
|
1477
|
pWDTC->WDTC_WDCR = 0xA5000001;
|
|
1478
|
}
|
|
1479
|
|
|
1480
|
//*----------------------------------------------------------------------------
|
|
1481
|
//* \fn AT91F_WDTSGettatus
|
|
1482
|
//* \brief Get Watchdog Status
|
|
1483
|
//*----------------------------------------------------------------------------
|
|
1484
|
static inline unsigned int AT91F_WDTSGettatus(
|
|
1485
|
AT91PS_WDTC pWDTC)
|
|
1486
|
{
|
|
1487
|
return(pWDTC->WDTC_WDSR & 0x3);
|
|
1488
|
}
|
|
1489
|
|
|
1490
|
//*----------------------------------------------------------------------------
|
|
1491
|
//* \fn AT91F_WDTGetPeriod
|
|
1492
|
//* \brief Translate ms into Watchdog Compatible value
|
|
1493
|
//*----------------------------------------------------------------------------
|
|
1494
|
static inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
|
|
1495
|
{
|
|
1496
|
if ((ms < 4) || (ms > 16000))
|
|
1497
|
return 0;
|
|
1498
|
return((ms << 8) / 1000);
|
|
1499
|
}
|
|
1500
|
/* *****************************************************************************
|
|
1501
|
SOFTWARE API FOR VREG
|
|
1502
|
***************************************************************************** */
|
|
1503
|
//*----------------------------------------------------------------------------
|
|
1504
|
//* \fn AT91F_VREG_Enable_LowPowerMode
|
|
1505
|
//* \brief Enable VREG Low Power Mode
|
|
1506
|
//*----------------------------------------------------------------------------
|
|
1507
|
static inline void AT91F_VREG_Enable_LowPowerMode(
|
|
1508
|
AT91PS_VREG pVREG)
|
|
1509
|
{
|
|
1510
|
pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
|
|
1511
|
}
|
|
1512
|
|
|
1513
|
//*----------------------------------------------------------------------------
|
|
1514
|
//* \fn AT91F_VREG_Disable_LowPowerMode
|
|
1515
|
//* \brief Disable VREG Low Power Mode
|
|
1516
|
//*----------------------------------------------------------------------------
|
|
1517
|
static inline void AT91F_VREG_Disable_LowPowerMode(
|
|
1518
|
AT91PS_VREG pVREG)
|
|
1519
|
{
|
|
1520
|
pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
|
|
1521
|
}/* *****************************************************************************
|
|
1522
|
SOFTWARE API FOR MC
|
|
1523
|
***************************************************************************** */
|
|
1524
|
|
|
1525
|
#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
|
|
1526
|
|
|
1527
|
//*----------------------------------------------------------------------------
|
|
1528
|
//* \fn AT91F_MC_Remap
|
|
1529
|
//* \brief Make Remap
|
|
1530
|
//*----------------------------------------------------------------------------
|
|
1531
|
static inline void AT91F_MC_Remap (void) //
|
|
1532
|
{
|
|
1533
|
AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
|
|
1534
|
|
|
1535
|
pMC->MC_RCR = AT91C_MC_RCB;
|
|
1536
|
}
|
|
1537
|
|
|
1538
|
//*----------------------------------------------------------------------------
|
|
1539
|
//* \fn AT91F_MC_EFC_CfgModeReg
|
|
1540
|
//* \brief Configure the EFC Mode Register of the MC controller
|
|
1541
|
//*----------------------------------------------------------------------------
|
|
1542
|
static inline void AT91F_MC_EFC_CfgModeReg (
|
|
1543
|
AT91PS_MC pMC, // pointer to a MC controller
|
|
1544
|
unsigned int mode) // mode register
|
|
1545
|
{
|
|
1546
|
// Write to the FMR register
|
|
1547
|
pMC->MC_FMR = mode;
|
|
1548
|
}
|
|
1549
|
|
|
1550
|
//*----------------------------------------------------------------------------
|
|
1551
|
//* \fn AT91F_MC_EFC_GetModeReg
|
|
1552
|
//* \brief Return MC EFC Mode Regsiter
|
|
1553
|
//*----------------------------------------------------------------------------
|
|
1554
|
static inline unsigned int AT91F_MC_EFC_GetModeReg(
|
|
1555
|
AT91PS_MC pMC) // pointer to a MC controller
|
|
1556
|
{
|
|
1557
|
return pMC->MC_FMR;
|
|
1558
|
}
|
|
1559
|
|
|
1560
|
//*----------------------------------------------------------------------------
|
|
1561
|
//* \fn AT91F_MC_EFC_ComputeFMCN
|
|
1562
|
//* \brief Return MC EFC Mode Regsiter
|
|
1563
|
//*----------------------------------------------------------------------------
|
|
1564
|
static inline unsigned int AT91F_MC_EFC_ComputeFMCN(
|
|
1565
|
int master_clock) // master clock in Hz
|
|
1566
|
{
|
|
1567
|
return (master_clock/1000000 +2);
|
|
1568
|
}
|
|
1569
|
|
|
1570
|
//*----------------------------------------------------------------------------
|
|
1571
|
//* \fn AT91F_MC_EFC_PerformCmd
|
|
1572
|
//* \brief Perform EFC Command
|
|
1573
|
//*----------------------------------------------------------------------------
|
|
1574
|
static inline void AT91F_MC_EFC_PerformCmd (
|
|
1575
|
AT91PS_MC pMC, // pointer to a MC controller
|
|
1576
|
unsigned int transfer_cmd)
|
|
1577
|
{
|
|
1578
|
pMC->MC_FCR = transfer_cmd;
|
|
1579
|
}
|
|
1580
|
|
|
1581
|
//*----------------------------------------------------------------------------
|
|
1582
|
//* \fn AT91F_MC_EFC_GetStatus
|
|
1583
|
//* \brief Return MC EFC Status
|
|
1584
|
//*----------------------------------------------------------------------------
|
|
1585
|
static inline unsigned int AT91F_MC_EFC_GetStatus(
|
|
1586
|
AT91PS_MC pMC) // pointer to a MC controller
|
|
1587
|
{
|
|
1588
|
return pMC->MC_FSR;
|
|
1589
|
}
|
|
1590
|
|
|
1591
|
//*----------------------------------------------------------------------------
|
|
1592
|
//* \fn AT91F_MC_EFC_IsInterruptMasked
|
|
1593
|
//* \brief Test if EFC MC Interrupt is Masked
|
|
1594
|
//*----------------------------------------------------------------------------
|
|
1595
|
static inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
|
|
1596
|
AT91PS_MC pMC, // \arg pointer to a MC controller
|
|
1597
|
unsigned int flag) // \arg flag to be tested
|
|
1598
|
{
|
|
1599
|
return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
|
|
1600
|
}
|
|
1601
|
|
|
1602
|
//*----------------------------------------------------------------------------
|
|
1603
|
//* \fn AT91F_MC_EFC_IsInterruptSet
|
|
1604
|
//* \brief Test if EFC MC Interrupt is Set
|
|
1605
|
//*----------------------------------------------------------------------------
|
|
1606
|
static inline unsigned int AT91F_MC_EFC_IsInterruptSet(
|
|
1607
|
AT91PS_MC pMC, // \arg pointer to a MC controller
|
|
1608
|
unsigned int flag) // \arg flag to be tested
|
|
1609
|
{
|
|
1610
|
return (AT91F_MC_EFC_GetStatus(pMC) & flag);
|
|
1611
|
}
|
|
1612
|
|
|
1613
|
/* *****************************************************************************
|
|
1614
|
SOFTWARE API FOR SPI
|
|
1615
|
***************************************************************************** */
|
|
1616
|
//*----------------------------------------------------------------------------
|
|
1617
|
//* \fn AT91F_SPI_CfgCs
|
|
1618
|
//* \brief Configure SPI chip select register
|
|
1619
|
//*----------------------------------------------------------------------------
|
|
1620
|
static inline void AT91F_SPI_CfgCs (
|
|
1621
|
AT91PS_SPI pSPI, // pointer to a SPI controller
|
|
1622
|
int cs, // SPI cs number (0 to 3)
|
|
1623
|
int val) // chip select register
|
|
1624
|
{
|
|
1625
|
//* Write to the CSR register
|
|
1626
|
*(pSPI->SPI_CSR + cs) = val;
|
|
1627
|
}
|
|
1628
|
|
|
1629
|
//*----------------------------------------------------------------------------
|
|
1630
|
//* \fn AT91F_SPI_EnableIt
|
|
1631
|
//* \brief Enable SPI interrupt
|
|
1632
|
//*----------------------------------------------------------------------------
|
|
1633
|
static inline void AT91F_SPI_EnableIt (
|
|
1634
|
AT91PS_SPI pSPI, // pointer to a SPI controller
|
|
1635
|
unsigned int flag) // IT to be enabled
|
|
1636
|
{
|
|
1637
|
//* Write to the IER register
|
|
1638
|
pSPI->SPI_IER = flag;
|
|
1639
|
}
|
|
1640
|
|
|
1641
|
//*----------------------------------------------------------------------------
|
|
1642
|
//* \fn AT91F_SPI_DisableIt
|
|
1643
|
//* \brief Disable SPI interrupt
|
|
1644
|
//*----------------------------------------------------------------------------
|
|
1645
|
static inline void AT91F_SPI_DisableIt (
|
|
1646
|
AT91PS_SPI pSPI, // pointer to a SPI controller
|
|
1647
|
unsigned int flag) // IT to be disabled
|
|
1648
|
{
|
|
1649
|
//* Write to the IDR register
|
|
1650
|
pSPI->SPI_IDR = flag;
|
|
1651
|
}
|
|
1652
|
|
|
1653
|
//*----------------------------------------------------------------------------
|
|
1654
|
//* \fn AT91F_SPI_Reset
|
|
1655
|
//* \brief Reset the SPI controller
|
|
1656
|
//*----------------------------------------------------------------------------
|
|
1657
|
static inline void AT91F_SPI_Reset (
|
|
1658
|
AT91PS_SPI pSPI // pointer to a SPI controller
|
|
1659
|
)
|
|
1660
|
{
|
|
1661
|
//* Write to the CR register
|
|
1662
|
pSPI->SPI_CR = AT91C_SPI_SWRST;
|
|
1663
|
}
|
|
1664
|
|
|
1665
|
//*----------------------------------------------------------------------------
|
|
1666
|
//* \fn AT91F_SPI_Enable
|
|
1667
|
//* \brief Enable the SPI controller
|
|
1668
|
//*----------------------------------------------------------------------------
|
|
1669
|
static inline void AT91F_SPI_Enable (
|
|
1670
|
AT91PS_SPI pSPI // pointer to a SPI controller
|
|
1671
|
)
|
|
1672
|
{
|
|
1673
|
//* Write to the CR register
|
|
1674
|
pSPI->SPI_CR = AT91C_SPI_SPIEN;
|
|
1675
|
}
|
|
1676
|
|
|
1677
|
//*----------------------------------------------------------------------------
|
|
1678
|
//* \fn AT91F_SPI_Disable
|
|
1679
|
//* \brief Disable the SPI controller
|
|
1680
|
//*----------------------------------------------------------------------------
|
|
1681
|
static inline void AT91F_SPI_Disable (
|
|
1682
|
AT91PS_SPI pSPI // pointer to a SPI controller
|
|
1683
|
)
|
|
1684
|
{
|
|
1685
|
//* Write to the CR register
|
|
1686
|
pSPI->SPI_CR = AT91C_SPI_SPIDIS;
|
|
1687
|
}
|
|
1688
|
|
|
1689
|
//*----------------------------------------------------------------------------
|
|
1690
|
//* \fn AT91F_SPI_CfgMode
|
|
1691
|
//* \brief Enable the SPI controller
|
|
1692
|
//*----------------------------------------------------------------------------
|
|
1693
|
static inline void AT91F_SPI_CfgMode (
|
|
1694
|
AT91PS_SPI pSPI, // pointer to a SPI controller
|
|
1695
|
int mode) // mode register
|
|
1696
|
{
|
|
1697
|
//* Write to the MR register
|
|
1698
|
pSPI->SPI_MR = mode;
|
|
1699
|
}
|
|
1700
|
|
|
1701
|
//*----------------------------------------------------------------------------
|
|
1702
|
//* \fn AT91F_SPI_CfgPCS
|
|
1703
|
//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
|
|
1704
|
//*----------------------------------------------------------------------------
|
|
1705
|
static inline void AT91F_SPI_CfgPCS (
|
|
1706
|
AT91PS_SPI pSPI, // pointer to a SPI controller
|
|
1707
|
char PCS_Device) // PCS of the Device
|
|
1708
|
{
|
|
1709
|
//* Write to the MR register
|
|
1710
|
pSPI->SPI_MR &= 0xFFF0FFFF;
|
|
1711
|
pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
|
|
1712
|
}
|
|
1713
|
|
|
1714
|
//*----------------------------------------------------------------------------
|
|
1715
|
//* \fn AT91F_SPI_ReceiveFrame
|
|
1716
|
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
|
|
1717
|
//*----------------------------------------------------------------------------
|
|
1718
|
static inline unsigned int AT91F_SPI_ReceiveFrame (
|
|
1719
|
AT91PS_SPI pSPI,
|
|
1720
|
unsigned char *pBuffer,
|
|
1721
|
unsigned int szBuffer,
|
|
1722
|
unsigned char *pNextBuffer,
|
|
1723
|
unsigned int szNextBuffer )
|
|
1724
|
{
|
|
1725
|
return AT91F_PDC_ReceiveFrame(
|
|
1726
|
(AT91PS_PDC) &(pSPI->SPI_RPR),
|
|
1727
|
pBuffer,
|
|
1728
|
szBuffer,
|
|
1729
|
pNextBuffer,
|
|
1730
|
szNextBuffer);
|
|
1731
|
}
|
|
1732
|
|
|
1733
|
//*----------------------------------------------------------------------------
|
|
1734
|
//* \fn AT91F_SPI_SendFrame
|
|
1735
|
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
|
|
1736
|
//*----------------------------------------------------------------------------
|
|
1737
|
static inline unsigned int AT91F_SPI_SendFrame(
|
|
1738
|
AT91PS_SPI pSPI,
|
|
1739
|
const unsigned char *pBuffer,
|
|
1740
|
unsigned int szBuffer,
|
|
1741
|
const unsigned char *pNextBuffer,
|
|
1742
|
unsigned int szNextBuffer )
|
|
1743
|
{
|
|
1744
|
return AT91F_PDC_SendFrame(
|
|
1745
|
(AT91PS_PDC) &(pSPI->SPI_RPR),
|
|
1746
|
pBuffer,
|
|
1747
|
szBuffer,
|
|
1748
|
pNextBuffer,
|
|
1749
|
szNextBuffer);
|
|
1750
|
}
|
|
1751
|
|
|
1752
|
//*----------------------------------------------------------------------------
|
|
1753
|
//* \fn AT91F_SPI_Close
|
|
1754
|
//* \brief Close SPI: disable IT disable transfert, close PDC
|
|
1755
|
//*----------------------------------------------------------------------------
|
|
1756
|
extern void AT91F_SPI_Close(AT91PS_SPI pSPI); // \arg pointer to a SPI controller
|
|
1757
|
|
|
1758
|
//*----------------------------------------------------------------------------
|
|
1759
|
//* \fn AT91F_SPI_PutChar
|
|
1760
|
//* \brief Send a character,does not check if ready to send
|
|
1761
|
//*----------------------------------------------------------------------------
|
|
1762
|
static inline void AT91F_SPI_PutChar (
|
|
1763
|
AT91PS_SPI pSPI,
|
|
1764
|
unsigned int character,
|
|
1765
|
unsigned int cs_number )
|
|
1766
|
{
|
|
1767
|
unsigned int value_for_cs;
|
|
1768
|
value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
|
|
1769
|
pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
|
|
1770
|
}
|
|
1771
|
|
|
1772
|
//*----------------------------------------------------------------------------
|
|
1773
|
//* \fn AT91F_SPI_GetChar
|
|
1774
|
//* \brief Receive a character,does not check if a character is available
|
|
1775
|
//*----------------------------------------------------------------------------
|
|
1776
|
static inline int AT91F_SPI_GetChar (
|
|
1777
|
const AT91PS_SPI pSPI)
|
|
1778
|
{
|
|
1779
|
return((pSPI->SPI_RDR) & 0xFFFF);
|
|
1780
|
}
|
|
1781
|
|
|
1782
|
//*----------------------------------------------------------------------------
|
|
1783
|
//* \fn AT91F_SPI_GetInterruptMaskStatus
|
|
1784
|
//* \brief Return SPI Interrupt Mask Status
|
|
1785
|
//*----------------------------------------------------------------------------
|
|
1786
|
static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
|
|
1787
|
AT91PS_SPI pSpi) // \arg pointer to a SPI controller
|
|
1788
|
{
|
|
1789
|
return pSpi->SPI_IMR;
|
|
1790
|
}
|
|
1791
|
|
|
1792
|
//*----------------------------------------------------------------------------
|
|
1793
|
//* \fn AT91F_SPI_IsInterruptMasked
|
|
1794
|
//* \brief Test if SPI Interrupt is Masked
|
|
1795
|
//*----------------------------------------------------------------------------
|
|
1796
|
static inline int AT91F_SPI_IsInterruptMasked(
|
|
1797
|
AT91PS_SPI pSpi, // \arg pointer to a SPI controller
|
|
1798
|
unsigned int flag) // \arg flag to be tested
|
|
1799
|
{
|
|
1800
|
return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
|
|
1801
|
}
|
|
1802
|
|
|
1803
|
/* *****************************************************************************
|
|
1804
|
SOFTWARE API FOR ADC
|
|
1805
|
***************************************************************************** */
|
|
1806
|
//*----------------------------------------------------------------------------
|
|
1807
|
//* \fn AT91F_ADC_EnableIt
|
|
1808
|
//* \brief Enable ADC interrupt
|
|
1809
|
//*----------------------------------------------------------------------------
|
|
1810
|
static inline void AT91F_ADC_EnableIt (
|
|
1811
|
AT91PS_ADC pADC, // pointer to a ADC controller
|
|
1812
|
unsigned int flag) // IT to be enabled
|
|
1813
|
{
|
|
1814
|
//* Write to the IER register
|
|
1815
|
pADC->ADC_IER = flag;
|
|
1816
|
}
|
|
1817
|
|
|
1818
|
//*----------------------------------------------------------------------------
|
|
1819
|
//* \fn AT91F_ADC_DisableIt
|
|
1820
|
//* \brief Disable ADC interrupt
|
|
1821
|
//*----------------------------------------------------------------------------
|
|
1822
|
static inline void AT91F_ADC_DisableIt (
|
|
1823
|
AT91PS_ADC pADC, // pointer to a ADC controller
|
|
1824
|
unsigned int flag) // IT to be disabled
|
|
1825
|
{
|
|
1826
|
//* Write to the IDR register
|
|
1827
|
pADC->ADC_IDR = flag;
|
|
1828
|
}
|
|
1829
|
|
|
1830
|
//*----------------------------------------------------------------------------
|
|
1831
|
//* \fn AT91F_ADC_GetStatus
|
|
1832
|
//* \brief Return ADC Interrupt Status
|
|
1833
|
//*----------------------------------------------------------------------------
|
|
1834
|
static inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
|
|
1835
|
AT91PS_ADC pADC) // pointer to a ADC controller
|
|
1836
|
{
|
|
1837
|
return pADC->ADC_SR;
|
|
1838
|
}
|
|
1839
|
|
|
1840
|
//*----------------------------------------------------------------------------
|
|
1841
|
//* \fn AT91F_ADC_GetInterruptMaskStatus
|
|
1842
|
//* \brief Return ADC Interrupt Mask Status
|
|
1843
|
//*----------------------------------------------------------------------------
|
|
1844
|
static inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
|
|
1845
|
AT91PS_ADC pADC) // pointer to a ADC controller
|
|
1846
|
{
|
|
1847
|
return pADC->ADC_IMR;
|
|
1848
|
}
|
|
1849
|
|
|
1850
|
//*----------------------------------------------------------------------------
|
|
1851
|
//* \fn AT91F_ADC_IsInterruptMasked
|
|
1852
|
//* \brief Test if ADC Interrupt is Masked
|
|
1853
|
//*----------------------------------------------------------------------------
|
|
1854
|
static inline unsigned int AT91F_ADC_IsInterruptMasked(
|
|
1855
|
AT91PS_ADC pADC, // \arg pointer to a ADC controller
|
|
1856
|
unsigned int flag) // \arg flag to be tested
|
|
1857
|
{
|
|
1858
|
return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
|
|
1859
|
}
|
|
1860
|
|
|
1861
|
//*----------------------------------------------------------------------------
|
|
1862
|
//* \fn AT91F_ADC_IsStatusSet
|
|
1863
|
//* \brief Test if ADC Status is Set
|
|
1864
|
//*----------------------------------------------------------------------------
|
|
1865
|
static inline unsigned int AT91F_ADC_IsStatusSet(
|
|
1866
|
AT91PS_ADC pADC, // \arg pointer to a ADC controller
|
|
1867
|
unsigned int flag) // \arg flag to be tested
|
|
1868
|
{
|
|
1869
|
return (AT91F_ADC_GetStatus(pADC) & flag);
|
|
1870
|
}
|
|
1871
|
|
|
1872
|
//*----------------------------------------------------------------------------
|
|
1873
|
//* \fn AT91F_ADC_CfgModeReg
|
|
1874
|
//* \brief Configure the Mode Register of the ADC controller
|
|
1875
|
//*----------------------------------------------------------------------------
|
|
1876
|
static inline void AT91F_ADC_CfgModeReg (
|
|
1877
|
AT91PS_ADC pADC, // pointer to a ADC controller
|
|
1878
|
unsigned int mode) // mode register
|
|
1879
|
{
|
|
1880
|
//* Write to the MR register
|
|
1881
|
pADC->ADC_MR = mode;
|
|
1882
|
}
|
|
1883
|
|
|
1884
|
//*----------------------------------------------------------------------------
|
|
1885
|
//* \fn AT91F_ADC_GetModeReg
|
|
1886
|
//* \brief Return the Mode Register of the ADC controller value
|
|
1887
|
//*----------------------------------------------------------------------------
|
|
1888
|
static inline unsigned int AT91F_ADC_GetModeReg (
|
|
1889
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
1890
|
)
|
|
1891
|
{
|
|
1892
|
return pADC->ADC_MR;
|
|
1893
|
}
|
|
1894
|
|
|
1895
|
//*----------------------------------------------------------------------------
|
|
1896
|
//* \fn AT91F_ADC_CfgTimings
|
|
1897
|
//* \brief Configure the different necessary timings of the ADC controller
|
|
1898
|
//*----------------------------------------------------------------------------
|
|
1899
|
extern void AT91F_ADC_CfgTimings (
|
|
1900
|
AT91PS_ADC pADC, // pointer to a ADC controller
|
|
1901
|
unsigned int mck_clock, // in MHz
|
|
1902
|
unsigned int adc_clock, // in MHz
|
|
1903
|
unsigned int startup_time, // in us
|
|
1904
|
unsigned int sample_and_hold_time); // in ns
|
|
1905
|
|
|
1906
|
//*----------------------------------------------------------------------------
|
|
1907
|
//* \fn AT91F_ADC_EnableChannel
|
|
1908
|
//* \brief Return ADC Timer Register Value
|
|
1909
|
//*----------------------------------------------------------------------------
|
|
1910
|
static inline void AT91F_ADC_EnableChannel (
|
|
1911
|
AT91PS_ADC pADC, // pointer to a ADC controller
|
|
1912
|
unsigned int channel) // mode register
|
|
1913
|
{
|
|
1914
|
//* Write to the CHER register
|
|
1915
|
pADC->ADC_CHER = channel;
|
|
1916
|
}
|
|
1917
|
|
|
1918
|
//*----------------------------------------------------------------------------
|
|
1919
|
//* \fn AT91F_ADC_DisableChannel
|
|
1920
|
//* \brief Return ADC Timer Register Value
|
|
1921
|
//*----------------------------------------------------------------------------
|
|
1922
|
static inline void AT91F_ADC_DisableChannel (
|
|
1923
|
AT91PS_ADC pADC, // pointer to a ADC controller
|
|
1924
|
unsigned int channel) // mode register
|
|
1925
|
{
|
|
1926
|
//* Write to the CHDR register
|
|
1927
|
pADC->ADC_CHDR = channel;
|
|
1928
|
}
|
|
1929
|
|
|
1930
|
//*----------------------------------------------------------------------------
|
|
1931
|
//* \fn AT91F_ADC_GetChannelStatus
|
|
1932
|
//* \brief Return ADC Timer Register Value
|
|
1933
|
//*----------------------------------------------------------------------------
|
|
1934
|
static inline unsigned int AT91F_ADC_GetChannelStatus (
|
|
1935
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
1936
|
)
|
|
1937
|
{
|
|
1938
|
return pADC->ADC_CHSR;
|
|
1939
|
}
|
|
1940
|
|
|
1941
|
//*----------------------------------------------------------------------------
|
|
1942
|
//* \fn AT91F_ADC_StartConversion
|
|
1943
|
//* \brief Software request for a analog to digital conversion
|
|
1944
|
//*----------------------------------------------------------------------------
|
|
1945
|
static inline void AT91F_ADC_StartConversion (
|
|
1946
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
1947
|
)
|
|
1948
|
{
|
|
1949
|
pADC->ADC_CR = AT91C_ADC_START;
|
|
1950
|
}
|
|
1951
|
|
|
1952
|
//*----------------------------------------------------------------------------
|
|
1953
|
//* \fn AT91F_ADC_SoftReset
|
|
1954
|
//* \brief Software reset
|
|
1955
|
//*----------------------------------------------------------------------------
|
|
1956
|
static inline void AT91F_ADC_SoftReset (
|
|
1957
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
1958
|
)
|
|
1959
|
{
|
|
1960
|
pADC->ADC_CR = AT91C_ADC_SWRST;
|
|
1961
|
}
|
|
1962
|
|
|
1963
|
//*----------------------------------------------------------------------------
|
|
1964
|
//* \fn AT91F_ADC_GetLastConvertedData
|
|
1965
|
//* \brief Return the Last Converted Data
|
|
1966
|
//*----------------------------------------------------------------------------
|
|
1967
|
static inline unsigned int AT91F_ADC_GetLastConvertedData (
|
|
1968
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
1969
|
)
|
|
1970
|
{
|
|
1971
|
return pADC->ADC_LCDR;
|
|
1972
|
}
|
|
1973
|
|
|
1974
|
//*----------------------------------------------------------------------------
|
|
1975
|
//* \fn AT91F_ADC_GetConvertedDataCH0
|
|
1976
|
//* \brief Return the Channel 0 Converted Data
|
|
1977
|
//*----------------------------------------------------------------------------
|
|
1978
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
|
|
1979
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
1980
|
)
|
|
1981
|
{
|
|
1982
|
return pADC->ADC_CDR0;
|
|
1983
|
}
|
|
1984
|
|
|
1985
|
//*----------------------------------------------------------------------------
|
|
1986
|
//* \fn AT91F_ADC_GetConvertedDataCH1
|
|
1987
|
//* \brief Return the Channel 1 Converted Data
|
|
1988
|
//*----------------------------------------------------------------------------
|
|
1989
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
|
|
1990
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
1991
|
)
|
|
1992
|
{
|
|
1993
|
return pADC->ADC_CDR1;
|
|
1994
|
}
|
|
1995
|
|
|
1996
|
//*----------------------------------------------------------------------------
|
|
1997
|
//* \fn AT91F_ADC_GetConvertedDataCH2
|
|
1998
|
//* \brief Return the Channel 2 Converted Data
|
|
1999
|
//*----------------------------------------------------------------------------
|
|
2000
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
|
|
2001
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
2002
|
)
|
|
2003
|
{
|
|
2004
|
return pADC->ADC_CDR2;
|
|
2005
|
}
|
|
2006
|
|
|
2007
|
//*----------------------------------------------------------------------------
|
|
2008
|
//* \fn AT91F_ADC_GetConvertedDataCH3
|
|
2009
|
//* \brief Return the Channel 3 Converted Data
|
|
2010
|
//*----------------------------------------------------------------------------
|
|
2011
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
|
|
2012
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
2013
|
)
|
|
2014
|
{
|
|
2015
|
return pADC->ADC_CDR3;
|
|
2016
|
}
|
|
2017
|
|
|
2018
|
//*----------------------------------------------------------------------------
|
|
2019
|
//* \fn AT91F_ADC_GetConvertedDataCH4
|
|
2020
|
//* \brief Return the Channel 4 Converted Data
|
|
2021
|
//*----------------------------------------------------------------------------
|
|
2022
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
|
|
2023
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
2024
|
)
|
|
2025
|
{
|
|
2026
|
return pADC->ADC_CDR4;
|
|
2027
|
}
|
|
2028
|
|
|
2029
|
//*----------------------------------------------------------------------------
|
|
2030
|
//* \fn AT91F_ADC_GetConvertedDataCH5
|
|
2031
|
//* \brief Return the Channel 5 Converted Data
|
|
2032
|
//*----------------------------------------------------------------------------
|
|
2033
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
|
|
2034
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
2035
|
)
|
|
2036
|
{
|
|
2037
|
return pADC->ADC_CDR5;
|
|
2038
|
}
|
|
2039
|
|
|
2040
|
//*----------------------------------------------------------------------------
|
|
2041
|
//* \fn AT91F_ADC_GetConvertedDataCH6
|
|
2042
|
//* \brief Return the Channel 6 Converted Data
|
|
2043
|
//*----------------------------------------------------------------------------
|
|
2044
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
|
|
2045
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
2046
|
)
|
|
2047
|
{
|
|
2048
|
return pADC->ADC_CDR6;
|
|
2049
|
}
|
|
2050
|
|
|
2051
|
//*----------------------------------------------------------------------------
|
|
2052
|
//* \fn AT91F_ADC_GetConvertedDataCH7
|
|
2053
|
//* \brief Return the Channel 7 Converted Data
|
|
2054
|
//*----------------------------------------------------------------------------
|
|
2055
|
static inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
|
|
2056
|
AT91PS_ADC pADC // pointer to a ADC controller
|
|
2057
|
)
|
|
2058
|
{
|
|
2059
|
return pADC->ADC_CDR7;
|
|
2060
|
}
|
|
2061
|
|
|
2062
|
/* *****************************************************************************
|
|
2063
|
SOFTWARE API FOR SSC
|
|
2064
|
***************************************************************************** */
|
|
2065
|
//* Define the standard I2S mode configuration
|
|
2066
|
|
|
2067
|
//* Configuration to set in the SSC Transmit Clock Mode Register
|
|
2068
|
//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
|
|
2069
|
//* nb_slot_by_frame : number of channels
|
|
2070
|
#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
|
|
2071
|
AT91C_SSC_CKS_DIV +\
|
|
2072
|
AT91C_SSC_CKO_CONTINOUS +\
|
|
2073
|
AT91C_SSC_CKG_NONE +\
|
|
2074
|
AT91C_SSC_START_FALL_RF +\
|
|
2075
|
AT91C_SSC_STTOUT +\
|
|
2076
|
((1<<16) & AT91C_SSC_STTDLY) +\
|
|
2077
|
((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
|
|
2078
|
|
|
2079
|
|
|
2080
|
//* Configuration to set in the SSC Transmit Frame Mode Register
|
|
2081
|
//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
|
|
2082
|
//* nb_slot_by_frame : number of channels
|
|
2083
|
#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
|
|
2084
|
(nb_bit_by_slot-1) +\
|
|
2085
|
AT91C_SSC_MSBF +\
|
|
2086
|
(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
|
|
2087
|
(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
|
|
2088
|
AT91C_SSC_FSOS_NEGATIVE)
|
|
2089
|
|
|
2090
|
|
|
2091
|
//*----------------------------------------------------------------------------
|
|
2092
|
//* \fn AT91F_SSC_SetBaudrate
|
|
2093
|
//* \brief Set the baudrate according to the CPU clock
|
|
2094
|
//*----------------------------------------------------------------------------
|
|
2095
|
extern void AT91F_SSC_SetBaudrate (
|
|
2096
|
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
|
|
2097
|
unsigned int mainClock, // \arg peripheral clock
|
|
2098
|
unsigned int speed); // \arg SSC baudrate
|
|
2099
|
|
|
2100
|
//*----------------------------------------------------------------------------
|
|
2101
|
//* \fn AT91F_SSC_Configure
|
|
2102
|
//* \brief Configure SSC
|
|
2103
|
//*----------------------------------------------------------------------------
|
|
2104
|
extern void AT91F_SSC_Configure (
|
|
2105
|
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
|
|
2106
|
unsigned int syst_clock, // \arg System Clock Frequency
|
|
2107
|
unsigned int baud_rate, // \arg Expected Baud Rate Frequency
|
|
2108
|
unsigned int clock_rx, // \arg Receiver Clock Parameters
|
|
2109
|
unsigned int mode_rx, // \arg mode Register to be programmed
|
|
2110
|
unsigned int clock_tx, // \arg Transmitter Clock Parameters
|
|
2111
|
unsigned int mode_tx); // \arg mode Register to be programmed
|
|
2112
|
|
|
2113
|
//*----------------------------------------------------------------------------
|
|
2114
|
//* \fn AT91F_SSC_EnableRx
|
|
2115
|
//* \brief Enable receiving datas
|
|
2116
|
//*----------------------------------------------------------------------------
|
|
2117
|
static inline void AT91F_SSC_EnableRx (
|
|
2118
|
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
|
|
2119
|
{
|
|
2120
|
//* Enable receiver
|
|
2121
|
pSSC->SSC_CR = AT91C_SSC_RXEN;
|
|
2122
|
}
|
|
2123
|
|
|
2124
|
//*----------------------------------------------------------------------------
|
|
2125
|
//* \fn AT91F_SSC_DisableRx
|
|
2126
|
//* \brief Disable receiving datas
|
|
2127
|
//*----------------------------------------------------------------------------
|
|
2128
|
static inline void AT91F_SSC_DisableRx (
|
|
2129
|
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
|
|
2130
|
{
|
|
2131
|
//* Disable receiver
|
|
2132
|
pSSC->SSC_CR = AT91C_SSC_RXDIS;
|
|
2133
|
}
|
|
2134
|
|
|
2135
|
//*----------------------------------------------------------------------------
|
|
2136
|
//* \fn AT91F_SSC_EnableTx
|
|
2137
|
//* \brief Enable sending datas
|
|
2138
|
//*----------------------------------------------------------------------------
|
|
2139
|
static inline void AT91F_SSC_EnableTx (
|
|
2140
|
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
|
|
2141
|
{
|
|
2142
|
//* Enable transmitter
|
|
2143
|
pSSC->SSC_CR = AT91C_SSC_TXEN;
|
|
2144
|
}
|
|
2145
|
|
|
2146
|
//*----------------------------------------------------------------------------
|
|
2147
|
//* \fn AT91F_SSC_DisableTx
|
|
2148
|
//* \brief Disable sending datas
|
|
2149
|
//*----------------------------------------------------------------------------
|
|
2150
|
static inline void AT91F_SSC_DisableTx (
|
|
2151
|
AT91PS_SSC pSSC) // \arg pointer to a SSC controller
|
|
2152
|
{
|
|
2153
|
//* Disable transmitter
|
|
2154
|
pSSC->SSC_CR = AT91C_SSC_TXDIS;
|
|
2155
|
}
|
|
2156
|
|
|
2157
|
//*----------------------------------------------------------------------------
|
|
2158
|
//* \fn AT91F_SSC_EnableIt
|
|
2159
|
//* \brief Enable SSC IT
|
|
2160
|
//*----------------------------------------------------------------------------
|
|
2161
|
static inline void AT91F_SSC_EnableIt (
|
|
2162
|
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
|
|
2163
|
unsigned int flag) // \arg IT to be enabled
|
|
2164
|
{
|
|
2165
|
//* Write to the IER register
|
|
2166
|
pSSC->SSC_IER = flag;
|
|
2167
|
}
|
|
2168
|
|
|
2169
|
//*----------------------------------------------------------------------------
|
|
2170
|
//* \fn AT91F_SSC_DisableIt
|
|
2171
|
//* \brief Disable SSC IT
|
|
2172
|
//*----------------------------------------------------------------------------
|
|
2173
|
static inline void AT91F_SSC_DisableIt (
|
|
2174
|
AT91PS_SSC pSSC, // \arg pointer to a SSC controller
|
|
2175
|
unsigned int flag) // \arg IT to be disabled
|
|
2176
|
{
|
|
2177
|
//* Write to the IDR register
|
|
2178
|
pSSC->SSC_IDR = flag;
|
|
2179
|
}
|
|
2180
|
|
|
2181
|
//*----------------------------------------------------------------------------
|
|
2182
|
//* \fn AT91F_SSC_ReceiveFrame
|
|
2183
|
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
|
|
2184
|
//*----------------------------------------------------------------------------
|
|
2185
|
static inline unsigned int AT91F_SSC_ReceiveFrame (
|
|
2186
|
AT91PS_SSC pSSC,
|
|
2187
|
unsigned char *pBuffer,
|
|
2188
|
unsigned int szBuffer,
|
|
2189
|
unsigned char *pNextBuffer,
|
|
2190
|
unsigned int szNextBuffer )
|
|
2191
|
{
|
|
2192
|
return AT91F_PDC_ReceiveFrame(
|
|
2193
|
(AT91PS_PDC) &(pSSC->SSC_RPR),
|
|
2194
|
pBuffer,
|
|
2195
|
szBuffer,
|
|
2196
|
pNextBuffer,
|
|
2197
|
szNextBuffer);
|
|
2198
|
}
|
|
2199
|
|
|
2200
|
//*----------------------------------------------------------------------------
|
|
2201
|
//* \fn AT91F_SSC_SendFrame
|
|
2202
|
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
|
|
2203
|
//*----------------------------------------------------------------------------
|
|
2204
|
static inline unsigned int AT91F_SSC_SendFrame(
|
|
2205
|
AT91PS_SSC pSSC,
|
|
2206
|
const unsigned char *pBuffer,
|
|
2207
|
unsigned int szBuffer,
|
|
2208
|
const unsigned char *pNextBuffer,
|
|
2209
|
unsigned int szNextBuffer )
|
|
2210
|
{
|
|
2211
|
return AT91F_PDC_SendFrame(
|
|
2212
|
(AT91PS_PDC) &(pSSC->SSC_RPR),
|
|
2213
|
pBuffer,
|
|
2214
|
szBuffer,
|
|
2215
|
pNextBuffer,
|
|
2216
|
szNextBuffer);
|
|
2217
|
}
|
|
2218
|
|
|
2219
|
//*----------------------------------------------------------------------------
|
|
2220
|
//* \fn AT91F_SSC_GetInterruptMaskStatus
|
|
2221
|
//* \brief Return SSC Interrupt Mask Status
|
|
2222
|
//*----------------------------------------------------------------------------
|
|
2223
|
static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
|
|
2224
|
AT91PS_SSC pSsc) // \arg pointer to a SSC controller
|
|
2225
|
{
|
|
2226
|
return pSsc->SSC_IMR;
|
|
2227
|
}
|
|
2228
|
|
|
2229
|
//*----------------------------------------------------------------------------
|
|
2230
|
//* \fn AT91F_SSC_IsInterruptMasked
|
|
2231
|
//* \brief Test if SSC Interrupt is Masked
|
|
2232
|
//*----------------------------------------------------------------------------
|
|
2233
|
static inline int AT91F_SSC_IsInterruptMasked(
|
|
2234
|
AT91PS_SSC pSsc, // \arg pointer to a SSC controller
|
|
2235
|
unsigned int flag) // \arg flag to be tested
|
|
2236
|
{
|
|
2237
|
return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
|
|
2238
|
}
|
|
2239
|
|
|
2240
|
/* *****************************************************************************
|
|
2241
|
SOFTWARE API FOR USART
|
|
2242
|
***************************************************************************** */
|
|
2243
|
//*----------------------------------------------------------------------------
|
|
2244
|
//* \fn AT91F_US_Baudrate
|
|
2245
|
//* \brief Calculate the baudrate
|
|
2246
|
//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
|
|
2247
|
#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
|
|
2248
|
AT91C_US_NBSTOP_1_BIT + \
|
|
2249
|
AT91C_US_PAR_NONE + \
|
|
2250
|
AT91C_US_CHRL_8_BITS + \
|
|
2251
|
AT91C_US_CLKS_CLOCK )
|
|
2252
|
|
|
2253
|
//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
|
|
2254
|
#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
|
|
2255
|
AT91C_US_NBSTOP_1_BIT + \
|
|
2256
|
AT91C_US_PAR_NONE + \
|
|
2257
|
AT91C_US_CHRL_8_BITS + \
|
|
2258
|
AT91C_US_CLKS_EXT )
|
|
2259
|
|
|
2260
|
//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
|
|
2261
|
#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
|
|
2262
|
AT91C_US_USMODE_NORMAL + \
|
|
2263
|
AT91C_US_NBSTOP_1_BIT + \
|
|
2264
|
AT91C_US_PAR_NONE + \
|
|
2265
|
AT91C_US_CHRL_8_BITS + \
|
|
2266
|
AT91C_US_CLKS_CLOCK )
|
|
2267
|
|
|
2268
|
//* SCK used Label
|
|
2269
|
#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
|
|
2270
|
|
|
2271
|
//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
|
|
2272
|
#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
|
|
2273
|
AT91C_US_CLKS_CLOCK +\
|
|
2274
|
AT91C_US_NBSTOP_1_BIT + \
|
|
2275
|
AT91C_US_PAR_EVEN + \
|
|
2276
|
AT91C_US_CHRL_8_BITS + \
|
|
2277
|
AT91C_US_CKLO +\
|
|
2278
|
AT91C_US_OVER)
|
|
2279
|
|
|
2280
|
//* Standard IRDA mode
|
|
2281
|
#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
|
|
2282
|
AT91C_US_NBSTOP_1_BIT + \
|
|
2283
|
AT91C_US_PAR_NONE + \
|
|
2284
|
AT91C_US_CHRL_8_BITS + \
|
|
2285
|
AT91C_US_CLKS_CLOCK )
|
|
2286
|
|
|
2287
|
//*----------------------------------------------------------------------------
|
|
2288
|
//* \fn AT91F_US_Baudrate
|
|
2289
|
//* \brief Caluculate baud_value according to the main clock and the baud rate
|
|
2290
|
//*----------------------------------------------------------------------------
|
|
2291
|
static inline unsigned int AT91F_US_Baudrate (
|
|
2292
|
const unsigned int main_clock, // \arg peripheral clock
|
|
2293
|
const unsigned int baud_rate) // \arg UART baudrate
|
|
2294
|
{
|
|
2295
|
unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
|
|
2296
|
if ((baud_value % 10) >= 5)
|
|
2297
|
baud_value = (baud_value / 10) + 1;
|
|
2298
|
else
|
|
2299
|
baud_value /= 10;
|
|
2300
|
return baud_value;
|
|
2301
|
}
|
|
2302
|
|
|
2303
|
//*----------------------------------------------------------------------------
|
|
2304
|
//* \fn AT91F_US_SetBaudrate
|
|
2305
|
//* \brief Set the baudrate according to the CPU clock
|
|
2306
|
//*----------------------------------------------------------------------------
|
|
2307
|
static inline void AT91F_US_SetBaudrate (
|
|
2308
|
AT91PS_USART pUSART, // \arg pointer to a USART controller
|
|
2309
|
unsigned int mainClock, // \arg peripheral clock
|
|
2310
|
unsigned int speed) // \arg UART baudrate
|
|
2311
|
{
|
|
2312
|
//* Define the baud rate divisor register
|
|
2313
|
pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
|
|
2314
|
}
|
|
2315
|
|
|
2316
|
//*----------------------------------------------------------------------------
|
|
2317
|
//* \fn AT91F_US_SetTimeguard
|
|
2318
|
//* \brief Set USART timeguard
|
|
2319
|
//*----------------------------------------------------------------------------
|
|
2320
|
static inline void AT91F_US_SetTimeguard (
|
|
2321
|
AT91PS_USART pUSART, // \arg pointer to a USART controller
|
|
2322
|
unsigned int timeguard) // \arg timeguard value
|
|
2323
|
{
|
|
2324
|
//* Write the Timeguard Register
|
|
2325
|
pUSART->US_TTGR = timeguard ;
|
|
2326
|
}
|
|
2327
|
|
|
2328
|
//*----------------------------------------------------------------------------
|
|
2329
|
//* \fn AT91F_US_EnableIt
|
|
2330
|
//* \brief Enable USART IT
|
|
2331
|
//*----------------------------------------------------------------------------
|
|
2332
|
static inline void AT91F_US_EnableIt (
|
|
2333
|
AT91PS_USART pUSART, // \arg pointer to a USART controller
|
|
2334
|
unsigned int flag) // \arg IT to be enabled
|
|
2335
|
{
|
|
2336
|
//* Write to the IER register
|
|
2337
|
pUSART->US_IER = flag;
|
|
2338
|
}
|
|
2339
|
|
|
2340
|
//*----------------------------------------------------------------------------
|
|
2341
|
//* \fn AT91F_US_DisableIt
|
|
2342
|
//* \brief Disable USART IT
|
|
2343
|
//*----------------------------------------------------------------------------
|
|
2344
|
static inline void AT91F_US_DisableIt (
|
|
2345
|
AT91PS_USART pUSART, // \arg pointer to a USART controller
|
|
2346
|
unsigned int flag) // \arg IT to be disabled
|
|
2347
|
{
|
|
2348
|
//* Write to the IER register
|
|
2349
|
pUSART->US_IDR = flag;
|
|
2350
|
}
|
|
2351
|
|
|
2352
|
//*----------------------------------------------------------------------------
|
|
2353
|
//* \fn AT91F_US_Configure
|
|
2354
|
//* \brief Configure USART
|
|
2355
|
//*----------------------------------------------------------------------------
|
|
2356
|
extern void AT91F_US_Configure (
|
|
2357
|
AT91PS_USART pUSART, // \arg pointer to a USART controller
|
|
2358
|
unsigned int mainClock, // \arg peripheral clock
|
|
2359
|
unsigned int mode , // \arg mode Register to be programmed
|
|
2360
|
unsigned int baudRate , // \arg baudrate to be programmed
|
|
2361
|
unsigned int timeguard ); // \arg timeguard to be programmed
|
|
2362
|
|
|
2363
|
//*----------------------------------------------------------------------------
|
|
2364
|
//* \fn AT91F_US_EnableRx
|
|
2365
|
//* \brief Enable receiving characters
|
|
2366
|
//*----------------------------------------------------------------------------
|
|
2367
|
static inline void AT91F_US_EnableRx (
|
|
2368
|
AT91PS_USART pUSART) // \arg pointer to a USART controller
|
|
2369
|
{
|
|
2370
|
//* Enable receiver
|
|
2371
|
pUSART->US_CR = AT91C_US_RXEN;
|
|
2372
|
}
|
|
2373
|
|
|
2374
|
//*----------------------------------------------------------------------------
|
|
2375
|
//* \fn AT91F_US_EnableTx
|
|
2376
|
//* \brief Enable sending characters
|
|
2377
|
//*----------------------------------------------------------------------------
|
|
2378
|
static inline void AT91F_US_EnableTx (
|
|
2379
|
AT91PS_USART pUSART) // \arg pointer to a USART controller
|
|
2380
|
{
|
|
2381
|
//* Enable transmitter
|
|
2382
|
pUSART->US_CR = AT91C_US_TXEN;
|
|
2383
|
}
|
|
2384
|
|
|
2385
|
//*----------------------------------------------------------------------------
|
|
2386
|
//* \fn AT91F_US_ResetRx
|
|
2387
|
//* \brief Reset Receiver and re-enable it
|
|
2388
|
//*----------------------------------------------------------------------------
|
|
2389
|
static inline void AT91F_US_ResetRx (
|
|
2390
|
AT91PS_USART pUSART) // \arg pointer to a USART controller
|
|
2391
|
{
|
|
2392
|
//* Reset receiver
|
|
2393
|
pUSART->US_CR = AT91C_US_RSTRX;
|
|
2394
|
//* Re-Enable receiver
|
|
2395
|
pUSART->US_CR = AT91C_US_RXEN;
|
|
2396
|
}
|
|
2397
|
|
|
2398
|
//*----------------------------------------------------------------------------
|
|
2399
|
//* \fn AT91F_US_ResetTx
|
|
2400
|
//* \brief Reset Transmitter and re-enable it
|
|
2401
|
//*----------------------------------------------------------------------------
|
|
2402
|
static inline void AT91F_US_ResetTx (
|
|
2403
|
AT91PS_USART pUSART) // \arg pointer to a USART controller
|
|
2404
|
{
|
|
2405
|
//* Reset transmitter
|
|
2406
|
pUSART->US_CR = AT91C_US_RSTTX;
|
|
2407
|
//* Enable transmitter
|
|
2408
|
pUSART->US_CR = AT91C_US_TXEN;
|
|
2409
|
}
|
|
2410
|
|
|
2411
|
//*----------------------------------------------------------------------------
|
|
2412
|
//* \fn AT91F_US_DisableRx
|
|
2413
|
//* \brief Disable Receiver
|
|
2414
|
//*----------------------------------------------------------------------------
|
|
2415
|
static inline void AT91F_US_DisableRx (
|
|
2416
|
AT91PS_USART pUSART) // \arg pointer to a USART controller
|
|
2417
|
{
|
|
2418
|
//* Disable receiver
|
|
2419
|
pUSART->US_CR = AT91C_US_RXDIS;
|
|
2420
|
}
|
|
2421
|
|
|
2422
|
//*----------------------------------------------------------------------------
|
|
2423
|
//* \fn AT91F_US_DisableTx
|
|
2424
|
//* \brief Disable Transmitter
|
|
2425
|
//*----------------------------------------------------------------------------
|
|
2426
|
static inline void AT91F_US_DisableTx (
|
|
2427
|
AT91PS_USART pUSART) // \arg pointer to a USART controller
|
|
2428
|
{
|
|
2429
|
//* Disable transmitter
|
|
2430
|
pUSART->US_CR = AT91C_US_TXDIS;
|
|
2431
|
}
|
|
2432
|
|
|
2433
|
//*----------------------------------------------------------------------------
|
|
2434
|
//* \fn AT91F_US_Close
|
|
2435
|
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
|
|
2436
|
//*----------------------------------------------------------------------------
|
|
2437
|
extern void AT91F_US_Close(AT91PS_USART pUSART); // \arg pointer to a USART controller
|
|
2438
|
|
|
2439
|
//*----------------------------------------------------------------------------
|
|
2440
|
//* \fn AT91F_US_TxReady
|
|
2441
|
//* \brief Return 1 if a character can be written in US_THR
|
|
2442
|
//*----------------------------------------------------------------------------
|
|
2443
|
static inline unsigned int AT91F_US_TxReady (
|
|
2444
|
AT91PS_USART pUSART ) // \arg pointer to a USART controller
|
|
2445
|
{
|
|
2446
|
return (pUSART->US_CSR & AT91C_US_TXRDY);
|
|
2447
|
}
|
|
2448
|
|
|
2449
|
//*----------------------------------------------------------------------------
|
|
2450
|
//* \fn AT91F_US_RxReady
|
|
2451
|
//* \brief Return 1 if a character can be read in US_RHR
|
|
2452
|
//*----------------------------------------------------------------------------
|
|
2453
|
static inline unsigned int AT91F_US_RxReady (
|
|
2454
|
AT91PS_USART pUSART ) // \arg pointer to a USART controller
|
|
2455
|
{
|
|
2456
|
return (pUSART->US_CSR & AT91C_US_RXRDY);
|
|
2457
|
}
|
|
2458
|
|
|
2459
|
//*----------------------------------------------------------------------------
|
|
2460
|
//* \fn AT91F_US_Error
|
|
2461
|
//* \brief Return the error flag
|
|
2462
|
//*----------------------------------------------------------------------------
|
|
2463
|
static inline unsigned int AT91F_US_Error (
|
|
2464
|
AT91PS_USART pUSART ) // \arg pointer to a USART controller
|
|
2465
|
{
|
|
2466
|
return (pUSART->US_CSR &
|
|
2467
|
(AT91C_US_OVRE | // Overrun error
|
|
2468
|
AT91C_US_FRAME | // Framing error
|
|
2469
|
AT91C_US_PARE)); // Parity error
|
|
2470
|
}
|
|
2471
|
|
|
2472
|
//*----------------------------------------------------------------------------
|
|
2473
|
//* \fn AT91F_US_PutChar
|
|
2474
|
//* \brief Send a character,does not check if ready to send
|
|
2475
|
//*----------------------------------------------------------------------------
|
|
2476
|
static inline void AT91F_US_PutChar (
|
|
2477
|
AT91PS_USART pUSART,
|
|
2478
|
int character )
|
|
2479
|
{
|
|
2480
|
pUSART->US_THR = (character & 0x1FF);
|
|
2481
|
}
|
|
2482
|
|
|
2483
|
//*----------------------------------------------------------------------------
|
|
2484
|
//* \fn AT91F_US_GetChar
|
|
2485
|
//* \brief Receive a character,does not check if a character is available
|
|
2486
|
//*----------------------------------------------------------------------------
|
|
2487
|
static inline int AT91F_US_GetChar (
|
|
2488
|
const AT91PS_USART pUSART)
|
|
2489
|
{
|
|
2490
|
return((pUSART->US_RHR) & 0x1FF);
|
|
2491
|
}
|
|
2492
|
|
|
2493
|
//*----------------------------------------------------------------------------
|
|
2494
|
//* \fn AT91F_US_SendFrame
|
|
2495
|
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
|
|
2496
|
//*----------------------------------------------------------------------------
|
|
2497
|
static inline unsigned int AT91F_US_SendFrame(
|
|
2498
|
AT91PS_USART pUSART,
|
|
2499
|
const unsigned char *pBuffer,
|
|
2500
|
unsigned int szBuffer,
|
|
2501
|
const unsigned char *pNextBuffer,
|
|
2502
|
unsigned int szNextBuffer )
|
|
2503
|
{
|
|
2504
|
return AT91F_PDC_SendFrame(
|
|
2505
|
(AT91PS_PDC) &(pUSART->US_RPR),
|
|
2506
|
pBuffer,
|
|
2507
|
szBuffer,
|
|
2508
|
pNextBuffer,
|
|
2509
|
szNextBuffer);
|
|
2510
|
}
|
|
2511
|
|
|
2512
|
//*----------------------------------------------------------------------------
|
|
2513
|
//* \fn AT91F_US_ReceiveFrame
|
|
2514
|
//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
|
|
2515
|
//*----------------------------------------------------------------------------
|
|
2516
|
static inline unsigned int AT91F_US_ReceiveFrame (
|
|
2517
|
AT91PS_USART pUSART,
|
|
2518
|
unsigned char *pBuffer,
|
|
2519
|
unsigned int szBuffer,
|
|
2520
|
unsigned char *pNextBuffer,
|
|
2521
|
unsigned int szNextBuffer )
|
|
2522
|
{
|
|
2523
|
return AT91F_PDC_ReceiveFrame(
|
|
2524
|
(AT91PS_PDC) &(pUSART->US_RPR),
|
|
2525
|
pBuffer,
|
|
2526
|
szBuffer,
|
|
2527
|
pNextBuffer,
|
|
2528
|
szNextBuffer);
|
|
2529
|
}
|
|
2530
|
|
|
2531
|
//*----------------------------------------------------------------------------
|
|
2532
|
//* \fn AT91F_US_SetIrdaFilter
|
|
2533
|
//* \brief Set the value of IrDa filter tregister
|
|
2534
|
//*----------------------------------------------------------------------------
|
|
2535
|
static inline void AT91F_US_SetIrdaFilter (
|
|
2536
|
AT91PS_USART pUSART,
|
|
2537
|
unsigned char value
|
|
2538
|
)
|
|
2539
|
{
|
|
2540
|
pUSART->US_IF = value;
|
|
2541
|
}
|
|
2542
|
|
|
2543
|
/* *****************************************************************************
|
|
2544
|
SOFTWARE API FOR TWI
|
|
2545
|
***************************************************************************** */
|
|
2546
|
//*----------------------------------------------------------------------------
|
|
2547
|
//* \fn AT91F_TWI_EnableIt
|
|
2548
|
//* \brief Enable TWI IT
|
|
2549
|
//*----------------------------------------------------------------------------
|
|
2550
|
static inline void AT91F_TWI_EnableIt (
|
|
2551
|
AT91PS_TWI pTWI, // \arg pointer to a TWI controller
|
|
2552
|
unsigned int flag) // \arg IT to be enabled
|
|
2553
|
{
|
|
2554
|
//* Write to the IER register
|
|
2555
|
pTWI->TWI_IER = flag;
|
|
2556
|
}
|
|
2557
|
|
|
2558
|
//*----------------------------------------------------------------------------
|
|
2559
|
//* \fn AT91F_TWI_DisableIt
|
|
2560
|
//* \brief Disable TWI IT
|
|
2561
|
//*----------------------------------------------------------------------------
|
|
2562
|
static inline void AT91F_TWI_DisableIt (
|
|
2563
|
AT91PS_TWI pTWI, // \arg pointer to a TWI controller
|
|
2564
|
unsigned int flag) // \arg IT to be disabled
|
|
2565
|
{
|
|
2566
|
//* Write to the IDR register
|
|
2567
|
pTWI->TWI_IDR = flag;
|
|
2568
|
}
|
|
2569
|
|
|
2570
|
//*----------------------------------------------------------------------------
|
|
2571
|
//* \fn AT91F_TWI_Configure
|
|
2572
|
//* \brief Configure TWI in master mode
|
|
2573
|
//*----------------------------------------------------------------------------
|
|
2574
|
static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
|
|
2575
|
{
|
|
2576
|
//* Disable interrupts
|
|
2577
|
pTWI->TWI_IDR = (unsigned int) -1;
|
|
2578
|
|
|
2579
|
//* Reset peripheral
|
|
2580
|
pTWI->TWI_CR = AT91C_TWI_SWRST;
|
|
2581
|
|
|
2582
|
//* Set Master mode
|
|
2583
|
pTWI->TWI_CR = AT91C_TWI_MSEN;
|
|
2584
|
|
|
2585
|
}
|
|
2586
|
|
|
2587
|
//*----------------------------------------------------------------------------
|
|
2588
|
//* \fn AT91F_TWI_GetInterruptMaskStatus
|
|
2589
|
//* \brief Return TWI Interrupt Mask Status
|
|
2590
|
//*----------------------------------------------------------------------------
|
|
2591
|
static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
|
|
2592
|
AT91PS_TWI pTwi) // \arg pointer to a TWI controller
|
|
2593
|
{
|
|
2594
|
return pTwi->TWI_IMR;
|
|
2595
|
}
|
|
2596
|
|
|
2597
|
//*----------------------------------------------------------------------------
|
|
2598
|
//* \fn AT91F_TWI_IsInterruptMasked
|
|
2599
|
//* \brief Test if TWI Interrupt is Masked
|
|
2600
|
//*----------------------------------------------------------------------------
|
|
2601
|
static inline int AT91F_TWI_IsInterruptMasked(
|
|
2602
|
AT91PS_TWI pTwi, // \arg pointer to a TWI controller
|
|
2603
|
unsigned int flag) // \arg flag to be tested
|
|
2604
|
{
|
|
2605
|
return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
|
|
2606
|
}
|
|
2607
|
|
|
2608
|
/* *****************************************************************************
|
|
2609
|
SOFTWARE API FOR TC
|
|
2610
|
***************************************************************************** */
|
|
2611
|
//*----------------------------------------------------------------------------
|
|
2612
|
//* \fn AT91F_TC_InterruptEnable
|
|
2613
|
//* \brief Enable TC Interrupt
|
|
2614
|
//*----------------------------------------------------------------------------
|
|
2615
|
static inline void AT91F_TC_InterruptEnable(
|
|
2616
|
AT91PS_TC pTc, // \arg pointer to a TC controller
|
|
2617
|
unsigned int flag) // \arg TC interrupt to be enabled
|
|
2618
|
{
|
|
2619
|
pTc->TC_IER = flag;
|
|
2620
|
}
|
|
2621
|
|
|
2622
|
//*----------------------------------------------------------------------------
|
|
2623
|
//* \fn AT91F_TC_InterruptDisable
|
|
2624
|
//* \brief Disable TC Interrupt
|
|
2625
|
//*----------------------------------------------------------------------------
|
|
2626
|
static inline void AT91F_TC_InterruptDisable(
|
|
2627
|
AT91PS_TC pTc, // \arg pointer to a TC controller
|
|
2628
|
unsigned int flag) // \arg TC interrupt to be disabled
|
|
2629
|
{
|
|
2630
|
pTc->TC_IDR = flag;
|
|
2631
|
}
|
|
2632
|
|
|
2633
|
//*----------------------------------------------------------------------------
|
|
2634
|
//* \fn AT91F_TC_GetInterruptMaskStatus
|
|
2635
|
//* \brief Return TC Interrupt Mask Status
|
|
2636
|
//*----------------------------------------------------------------------------
|
|
2637
|
static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
|
|
2638
|
AT91PS_TC pTc) // \arg pointer to a TC controller
|
|
2639
|
{
|
|
2640
|
return pTc->TC_IMR;
|
|
2641
|
}
|
|
2642
|
|
|
2643
|
//*----------------------------------------------------------------------------
|
|
2644
|
//* \fn AT91F_TC_IsInterruptMasked
|
|
2645
|
//* \brief Test if TC Interrupt is Masked
|
|
2646
|
//*----------------------------------------------------------------------------
|
|
2647
|
static inline int AT91F_TC_IsInterruptMasked(
|
|
2648
|
AT91PS_TC pTc, // \arg pointer to a TC controller
|
|
2649
|
unsigned int flag) // \arg flag to be tested
|
|
2650
|
{
|
|
2651
|
return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
|
|
2652
|
}
|
|
2653
|
|
|
2654
|
/* *****************************************************************************
|
|
2655
|
SOFTWARE API FOR PWMC
|
|
2656
|
***************************************************************************** */
|
|
2657
|
//*----------------------------------------------------------------------------
|
|
2658
|
//* \fn AT91F_PWM_GetStatus
|
|
2659
|
//* \brief Return PWM Interrupt Status
|
|
2660
|
//*----------------------------------------------------------------------------
|
|
2661
|
static inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
|
|
2662
|
AT91PS_PWMC pPWM) // pointer to a PWM controller
|
|
2663
|
{
|
|
2664
|
return pPWM->PWMC_SR;
|
|
2665
|
}
|
|
2666
|
|
|
2667
|
//*----------------------------------------------------------------------------
|
|
2668
|
//* \fn AT91F_PWM_InterruptEnable
|
|
2669
|
//* \brief Enable PWM Interrupt
|
|
2670
|
//*----------------------------------------------------------------------------
|
|
2671
|
static inline void AT91F_PWMC_InterruptEnable(
|
|
2672
|
AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
|
|
2673
|
unsigned int flag) // \arg PWM interrupt to be enabled
|
|
2674
|
{
|
|
2675
|
pPwm->PWMC_IER = flag;
|
|
2676
|
}
|
|
2677
|
|
|
2678
|
//*----------------------------------------------------------------------------
|
|
2679
|
//* \fn AT91F_PWM_InterruptDisable
|
|
2680
|
//* \brief Disable PWM Interrupt
|
|
2681
|
//*----------------------------------------------------------------------------
|
|
2682
|
static inline void AT91F_PWMC_InterruptDisable(
|
|
2683
|
AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
|
|
2684
|
unsigned int flag) // \arg PWM interrupt to be disabled
|
|
2685
|
{
|
|
2686
|
pPwm->PWMC_IDR = flag;
|
|
2687
|
}
|
|
2688
|
|
|
2689
|
//*----------------------------------------------------------------------------
|
|
2690
|
//* \fn AT91F_PWM_GetInterruptMaskStatus
|
|
2691
|
//* \brief Return PWM Interrupt Mask Status
|
|
2692
|
//*----------------------------------------------------------------------------
|
|
2693
|
static inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
|
|
2694
|
AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
|
|
2695
|
{
|
|
2696
|
return pPwm->PWMC_IMR;
|
|
2697
|
}
|
|
2698
|
|
|
2699
|
//*----------------------------------------------------------------------------
|
|
2700
|
//* \fn AT91F_PWM_IsInterruptMasked
|
|
2701
|
//* \brief Test if PWM Interrupt is Masked
|
|
2702
|
//*----------------------------------------------------------------------------
|
|
2703
|
static inline unsigned int AT91F_PWMC_IsInterruptMasked(
|
|
2704
|
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
|
|
2705
|
unsigned int flag) // \arg flag to be tested
|
|
2706
|
{
|
|
2707
|
return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
|
|
2708
|
}
|
|
2709
|
|
|
2710
|
//*----------------------------------------------------------------------------
|
|
2711
|
//* \fn AT91F_PWM_IsStatusSet
|
|
2712
|
//* \brief Test if PWM Interrupt is Set
|
|
2713
|
//*----------------------------------------------------------------------------
|
|
2714
|
static inline unsigned int AT91F_PWMC_IsStatusSet(
|
|
2715
|
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
|
|
2716
|
unsigned int flag) // \arg flag to be tested
|
|
2717
|
{
|
|
2718
|
return (AT91F_PWMC_GetStatus(pPWM) & flag);
|
|
2719
|
}
|
|
2720
|
|
|
2721
|
//*----------------------------------------------------------------------------
|
|
2722
|
//* \fn AT91F_PWM_CfgChannel
|
|
2723
|
//* \brief Test if PWM Interrupt is Set
|
|
2724
|
//*----------------------------------------------------------------------------
|
|
2725
|
static inline void AT91F_PWMC_CfgChannel(
|
|
2726
|
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
|
|
2727
|
unsigned int channelId, // \arg PWM channel ID
|
|
2728
|
unsigned int mode, // \arg PWM mode
|
|
2729
|
unsigned int period, // \arg PWM period
|
|
2730
|
unsigned int duty) // \arg PWM duty cycle
|
|
2731
|
{
|
|
2732
|
pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
|
|
2733
|
pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
|
|
2734
|
pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
|
|
2735
|
}
|
|
2736
|
|
|
2737
|
//*----------------------------------------------------------------------------
|
|
2738
|
//* \fn AT91F_PWM_StartChannel
|
|
2739
|
//* \brief Enable channel
|
|
2740
|
//*----------------------------------------------------------------------------
|
|
2741
|
static inline void AT91F_PWMC_StartChannel(
|
|
2742
|
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
|
|
2743
|
unsigned int flag) // \arg Channels IDs to be enabled
|
|
2744
|
{
|
|
2745
|
pPWM->PWMC_ENA = flag;
|
|
2746
|
}
|
|
2747
|
|
|
2748
|
//*----------------------------------------------------------------------------
|
|
2749
|
//* \fn AT91F_PWM_StopChannel
|
|
2750
|
//* \brief Disable channel
|
|
2751
|
//*----------------------------------------------------------------------------
|
|
2752
|
static inline void AT91F_PWMC_StopChannel(
|
|
2753
|
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
|
|
2754
|
unsigned int flag) // \arg Channels IDs to be enabled
|
|
2755
|
{
|
|
2756
|
pPWM->PWMC_DIS = flag;
|
|
2757
|
}
|
|
2758
|
|
|
2759
|
//*----------------------------------------------------------------------------
|
|
2760
|
//* \fn AT91F_PWM_UpdateChannel
|
|
2761
|
//* \brief Update Period or Duty Cycle
|
|
2762
|
//*----------------------------------------------------------------------------
|
|
2763
|
static inline void AT91F_PWMC_UpdateChannel(
|
|
2764
|
AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
|
|
2765
|
unsigned int channelId, // \arg PWM channel ID
|
|
2766
|
unsigned int update) // \arg Channels IDs to be enabled
|
|
2767
|
{
|
|
2768
|
pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
|
|
2769
|
}
|
|
2770
|
|
|
2771
|
/* *****************************************************************************
|
|
2772
|
SOFTWARE API FOR UDP
|
|
2773
|
***************************************************************************** */
|
|
2774
|
//*----------------------------------------------------------------------------
|
|
2775
|
//* \fn AT91F_UDP_EnableIt
|
|
2776
|
//* \brief Enable UDP IT
|
|
2777
|
//*----------------------------------------------------------------------------
|
|
2778
|
static inline void AT91F_UDP_EnableIt (
|
|
2779
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2780
|
unsigned int flag) // \arg IT to be enabled
|
|
2781
|
{
|
|
2782
|
//* Write to the IER register
|
|
2783
|
pUDP->UDP_IER = flag;
|
|
2784
|
}
|
|
2785
|
|
|
2786
|
//*----------------------------------------------------------------------------
|
|
2787
|
//* \fn AT91F_UDP_DisableIt
|
|
2788
|
//* \brief Disable UDP IT
|
|
2789
|
//*----------------------------------------------------------------------------
|
|
2790
|
static inline void AT91F_UDP_DisableIt (
|
|
2791
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2792
|
unsigned int flag) // \arg IT to be disabled
|
|
2793
|
{
|
|
2794
|
//* Write to the IDR register
|
|
2795
|
pUDP->UDP_IDR = flag;
|
|
2796
|
}
|
|
2797
|
|
|
2798
|
//*----------------------------------------------------------------------------
|
|
2799
|
//* \fn AT91F_UDP_SetAddress
|
|
2800
|
//* \brief Set UDP functional address
|
|
2801
|
//*----------------------------------------------------------------------------
|
|
2802
|
static inline void AT91F_UDP_SetAddress (
|
|
2803
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2804
|
unsigned char address) // \arg new UDP address
|
|
2805
|
{
|
|
2806
|
pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
|
|
2807
|
}
|
|
2808
|
|
|
2809
|
//*----------------------------------------------------------------------------
|
|
2810
|
//* \fn AT91F_UDP_EnableEp
|
|
2811
|
//* \brief Enable Endpoint
|
|
2812
|
//*----------------------------------------------------------------------------
|
|
2813
|
static inline void AT91F_UDP_EnableEp (
|
|
2814
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2815
|
unsigned char endpoint) // \arg endpoint number
|
|
2816
|
{
|
|
2817
|
pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
|
|
2818
|
}
|
|
2819
|
|
|
2820
|
//*----------------------------------------------------------------------------
|
|
2821
|
//* \fn AT91F_UDP_DisableEp
|
|
2822
|
//* \brief Enable Endpoint
|
|
2823
|
//*----------------------------------------------------------------------------
|
|
2824
|
static inline void AT91F_UDP_DisableEp (
|
|
2825
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2826
|
unsigned char endpoint) // \arg endpoint number
|
|
2827
|
{
|
|
2828
|
pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
|
|
2829
|
}
|
|
2830
|
|
|
2831
|
//*----------------------------------------------------------------------------
|
|
2832
|
//* \fn AT91F_UDP_SetState
|
|
2833
|
//* \brief Set UDP Device state
|
|
2834
|
//*----------------------------------------------------------------------------
|
|
2835
|
static inline void AT91F_UDP_SetState (
|
|
2836
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2837
|
unsigned int flag) // \arg new UDP address
|
|
2838
|
{
|
|
2839
|
pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
|
|
2840
|
pUDP->UDP_GLBSTATE |= flag;
|
|
2841
|
}
|
|
2842
|
|
|
2843
|
//*----------------------------------------------------------------------------
|
|
2844
|
//* \fn AT91F_UDP_GetState
|
|
2845
|
//* \brief return UDP Device state
|
|
2846
|
//*----------------------------------------------------------------------------
|
|
2847
|
static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
|
|
2848
|
AT91PS_UDP pUDP) // \arg pointer to a UDP controller
|
|
2849
|
{
|
|
2850
|
return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
|
|
2851
|
}
|
|
2852
|
|
|
2853
|
//*----------------------------------------------------------------------------
|
|
2854
|
//* \fn AT91F_UDP_ResetEp
|
|
2855
|
//* \brief Reset UDP endpoint
|
|
2856
|
//*----------------------------------------------------------------------------
|
|
2857
|
static inline void AT91F_UDP_ResetEp ( // \return the UDP device state
|
|
2858
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2859
|
unsigned int flag) // \arg Endpoints to be reset
|
|
2860
|
{
|
|
2861
|
pUDP->UDP_RSTEP = flag;
|
|
2862
|
pUDP->UDP_RSTEP = 0;
|
|
2863
|
}
|
|
2864
|
|
|
2865
|
//*----------------------------------------------------------------------------
|
|
2866
|
//* \fn AT91F_UDP_EpStall
|
|
2867
|
//* \brief Endpoint will STALL requests
|
|
2868
|
//*----------------------------------------------------------------------------
|
|
2869
|
static inline void AT91F_UDP_EpStall(
|
|
2870
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2871
|
unsigned char endpoint) // \arg endpoint number
|
|
2872
|
{
|
|
2873
|
pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
|
|
2874
|
}
|
|
2875
|
|
|
2876
|
//*----------------------------------------------------------------------------
|
|
2877
|
//* \fn AT91F_UDP_EpWrite
|
|
2878
|
//* \brief Write value in the DPR
|
|
2879
|
//*----------------------------------------------------------------------------
|
|
2880
|
static inline void AT91F_UDP_EpWrite(
|
|
2881
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2882
|
unsigned char endpoint, // \arg endpoint number
|
|
2883
|
unsigned char value) // \arg value to be written in the DPR
|
|
2884
|
{
|
|
2885
|
pUDP->UDP_FDR[endpoint] = value;
|
|
2886
|
}
|
|
2887
|
|
|
2888
|
//*----------------------------------------------------------------------------
|
|
2889
|
//* \fn AT91F_UDP_EpRead
|
|
2890
|
//* \brief Return value from the DPR
|
|
2891
|
//*----------------------------------------------------------------------------
|
|
2892
|
static inline unsigned int AT91F_UDP_EpRead(
|
|
2893
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2894
|
unsigned char endpoint) // \arg endpoint number
|
|
2895
|
{
|
|
2896
|
return pUDP->UDP_FDR[endpoint];
|
|
2897
|
}
|
|
2898
|
|
|
2899
|
//*----------------------------------------------------------------------------
|
|
2900
|
//* \fn AT91F_UDP_EpEndOfWr
|
|
2901
|
//* \brief Notify the UDP that values in DPR are ready to be sent
|
|
2902
|
//*----------------------------------------------------------------------------
|
|
2903
|
static inline void AT91F_UDP_EpEndOfWr(
|
|
2904
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2905
|
unsigned char endpoint) // \arg endpoint number
|
|
2906
|
{
|
|
2907
|
pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
|
|
2908
|
}
|
|
2909
|
|
|
2910
|
//*----------------------------------------------------------------------------
|
|
2911
|
//* \fn AT91F_UDP_EpClear
|
|
2912
|
//* \brief Clear flag in the endpoint CSR register
|
|
2913
|
//*----------------------------------------------------------------------------
|
|
2914
|
static inline void AT91F_UDP_EpClear(
|
|
2915
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2916
|
unsigned char endpoint, // \arg endpoint number
|
|
2917
|
unsigned int flag) // \arg flag to be cleared
|
|
2918
|
{
|
|
2919
|
pUDP->UDP_CSR[endpoint] &= ~(flag);
|
|
2920
|
}
|
|
2921
|
|
|
2922
|
//*----------------------------------------------------------------------------
|
|
2923
|
//* \fn AT91F_UDP_EpSet
|
|
2924
|
//* \brief Set flag in the endpoint CSR register
|
|
2925
|
//*----------------------------------------------------------------------------
|
|
2926
|
static inline void AT91F_UDP_EpSet(
|
|
2927
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2928
|
unsigned char endpoint, // \arg endpoint number
|
|
2929
|
unsigned int flag) // \arg flag to be cleared
|
|
2930
|
{
|
|
2931
|
pUDP->UDP_CSR[endpoint] |= flag;
|
|
2932
|
}
|
|
2933
|
|
|
2934
|
//*----------------------------------------------------------------------------
|
|
2935
|
//* \fn AT91F_UDP_EpStatus
|
|
2936
|
//* \brief Return the endpoint CSR register
|
|
2937
|
//*----------------------------------------------------------------------------
|
|
2938
|
static inline unsigned int AT91F_UDP_EpStatus(
|
|
2939
|
AT91PS_UDP pUDP, // \arg pointer to a UDP controller
|
|
2940
|
unsigned char endpoint) // \arg endpoint number
|
|
2941
|
{
|
|
2942
|
return pUDP->UDP_CSR[endpoint];
|
|
2943
|
}
|
|
2944
|
|
|
2945
|
//*----------------------------------------------------------------------------
|
|
2946
|
//* \fn AT91F_UDP_GetInterruptMaskStatus
|
|
2947
|
//* \brief Return UDP Interrupt Mask Status
|
|
2948
|
//*----------------------------------------------------------------------------
|
|
2949
|
static inline unsigned int AT91F_UDP_GetInterruptMaskStatus(
|
|
2950
|
AT91PS_UDP pUdp) // \arg pointer to a UDP controller
|
|
2951
|
{
|
|
2952
|
return pUdp->UDP_IMR;
|
|
2953
|
}
|
|
2954
|
|
|
2955
|
//*----------------------------------------------------------------------------
|
|
2956
|
//* \fn AT91F_UDP_IsInterruptMasked
|
|
2957
|
//* \brief Test if UDP Interrupt is Masked
|
|
2958
|
//*----------------------------------------------------------------------------
|
|
2959
|
static inline int AT91F_UDP_IsInterruptMasked(
|
|
2960
|
AT91PS_UDP pUdp, // \arg pointer to a UDP controller
|
|
2961
|
unsigned int flag) // \arg flag to be tested
|
|
2962
|
{
|
|
2963
|
return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
|
|
2964
|
}
|
|
2965
|
|
|
2966
|
// ----------------------------------------------------------------------------
|
|
2967
|
// \fn AT91F_UDP_InterruptStatusRegister
|
|
2968
|
// \brief Return the Interrupt Status Register
|
|
2969
|
// ----------------------------------------------------------------------------
|
|
2970
|
static inline unsigned int AT91F_UDP_InterruptStatusRegister(
|
|
2971
|
AT91PS_UDP pUDP ) // \arg pointer to a UDP controller
|
|
2972
|
{
|
|
2973
|
return pUDP->UDP_ISR;
|
|
2974
|
}
|
|
2975
|
|
|
2976
|
// ----------------------------------------------------------------------------
|
|
2977
|
// \fn AT91F_UDP_InterruptClearRegister
|
|
2978
|
// \brief Clear Interrupt Register
|
|
2979
|
// ----------------------------------------------------------------------------
|
|
2980
|
static inline void AT91F_UDP_InterruptClearRegister (
|
|
2981
|
AT91PS_UDP pUDP, // \arg pointer to UDP controller
|
|
2982
|
unsigned int flag) // \arg IT to be cleat
|
|
2983
|
{
|
|
2984
|
pUDP->UDP_ICR = flag;
|
|
2985
|
}
|
|
2986
|
|
|
2987
|
// ----------------------------------------------------------------------------
|
|
2988
|
// \fn AT91F_UDP_EnableTransceiver
|
|
2989
|
// \brief Enable transceiver
|
|
2990
|
// ----------------------------------------------------------------------------
|
|
2991
|
static inline void AT91F_UDP_EnableTransceiver(
|
|
2992
|
AT91PS_UDP pUDP ) // \arg pointer to a UDP controller
|
|
2993
|
{
|
|
2994
|
pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS;
|
|
2995
|
}
|
|
2996
|
|
|
2997
|
// ----------------------------------------------------------------------------
|
|
2998
|
// \fn AT91F_UDP_DisableTransceiver
|
|
2999
|
// \brief Disable transceiver
|
|
3000
|
// ----------------------------------------------------------------------------
|
|
3001
|
static inline void AT91F_UDP_DisableTransceiver(
|
|
3002
|
AT91PS_UDP pUDP ) // \arg pointer to a UDP controller
|
|
3003
|
{
|
|
3004
|
pUDP->UDP_TXVC = AT91C_UDP_TXVDIS;
|
|
3005
|
}
|
|
3006
|
|
|
3007
|
//*----------------------------------------------------------------------------
|
|
3008
|
//* \fn AT91F_DBGU_CfgPMC
|
|
3009
|
//* \brief Enable Peripheral clock in PMC for DBGU
|
|
3010
|
//*----------------------------------------------------------------------------
|
|
3011
|
static inline void AT91F_DBGU_CfgPMC (void)
|
|
3012
|
{
|
|
3013
|
AT91F_PMC_EnablePeriphClock(
|
|
3014
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3015
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3016
|
}
|
|
3017
|
|
|
3018
|
//*----------------------------------------------------------------------------
|
|
3019
|
//* \fn AT91F_DBGU_CfgPIO
|
|
3020
|
//* \brief Configure PIO controllers to drive DBGU signals
|
|
3021
|
//*----------------------------------------------------------------------------
|
|
3022
|
static inline void AT91F_DBGU_CfgPIO (void)
|
|
3023
|
{
|
|
3024
|
// Configure PIO controllers to periph mode
|
|
3025
|
AT91F_PIO_CfgPeriph(
|
|
3026
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3027
|
((unsigned int) AT91C_PA9_DRXD ) |
|
|
3028
|
((unsigned int) AT91C_PA10_DTXD ), // Peripheral A
|
|
3029
|
0); // Peripheral B
|
|
3030
|
}
|
|
3031
|
|
|
3032
|
//*----------------------------------------------------------------------------
|
|
3033
|
//* \fn AT91F_PMC_CfgPMC
|
|
3034
|
//* \brief Enable Peripheral clock in PMC for PMC
|
|
3035
|
//*----------------------------------------------------------------------------
|
|
3036
|
static inline void AT91F_PMC_CfgPMC (void)
|
|
3037
|
{
|
|
3038
|
AT91F_PMC_EnablePeriphClock(
|
|
3039
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3040
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3041
|
}
|
|
3042
|
|
|
3043
|
//*----------------------------------------------------------------------------
|
|
3044
|
//* \fn AT91F_PMC_CfgPIO
|
|
3045
|
//* \brief Configure PIO controllers to drive PMC signals
|
|
3046
|
//*----------------------------------------------------------------------------
|
|
3047
|
static inline void AT91F_PMC_CfgPIO (void)
|
|
3048
|
{
|
|
3049
|
// Configure PIO controllers to periph mode
|
|
3050
|
AT91F_PIO_CfgPeriph(
|
|
3051
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3052
|
0, // Peripheral A
|
|
3053
|
((unsigned int) AT91C_PA6_PCK0 ) |
|
|
3054
|
((unsigned int) AT91C_PA18_PCK2 ) |
|
|
3055
|
((unsigned int) AT91C_PA31_PCK2 ) |
|
|
3056
|
((unsigned int) AT91C_PA21_PCK1 ) |
|
|
3057
|
((unsigned int) AT91C_PA17_PCK1 )); // Peripheral B
|
|
3058
|
}
|
|
3059
|
|
|
3060
|
//*----------------------------------------------------------------------------
|
|
3061
|
//* \fn AT91F_VREG_CfgPMC
|
|
3062
|
//* \brief Enable Peripheral clock in PMC for VREG
|
|
3063
|
//*----------------------------------------------------------------------------
|
|
3064
|
static inline void AT91F_VREG_CfgPMC (void)
|
|
3065
|
{
|
|
3066
|
AT91F_PMC_EnablePeriphClock(
|
|
3067
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3068
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3069
|
}
|
|
3070
|
|
|
3071
|
//*----------------------------------------------------------------------------
|
|
3072
|
//* \fn AT91F_RSTC_CfgPMC
|
|
3073
|
//* \brief Enable Peripheral clock in PMC for RSTC
|
|
3074
|
//*----------------------------------------------------------------------------
|
|
3075
|
static inline void AT91F_RSTC_CfgPMC (void)
|
|
3076
|
{
|
|
3077
|
AT91F_PMC_EnablePeriphClock(
|
|
3078
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3079
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3080
|
}
|
|
3081
|
|
|
3082
|
//*----------------------------------------------------------------------------
|
|
3083
|
//* \fn AT91F_SSC_CfgPMC
|
|
3084
|
//* \brief Enable Peripheral clock in PMC for SSC
|
|
3085
|
//*----------------------------------------------------------------------------
|
|
3086
|
static inline void AT91F_SSC_CfgPMC (void)
|
|
3087
|
{
|
|
3088
|
AT91F_PMC_EnablePeriphClock(
|
|
3089
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3090
|
((unsigned int) 1 << AT91C_ID_SSC));
|
|
3091
|
}
|
|
3092
|
|
|
3093
|
//*----------------------------------------------------------------------------
|
|
3094
|
//* \fn AT91F_SSC_CfgPIO
|
|
3095
|
//* \brief Configure PIO controllers to drive SSC signals
|
|
3096
|
//*----------------------------------------------------------------------------
|
|
3097
|
static inline void AT91F_SSC_CfgPIO (void)
|
|
3098
|
{
|
|
3099
|
// Configure PIO controllers to periph mode
|
|
3100
|
AT91F_PIO_CfgPeriph(
|
|
3101
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3102
|
((unsigned int) AT91C_PA19_RK ) |
|
|
3103
|
((unsigned int) AT91C_PA16_TK ) |
|
|
3104
|
((unsigned int) AT91C_PA15_TF ) |
|
|
3105
|
((unsigned int) AT91C_PA18_RD ) |
|
|
3106
|
((unsigned int) AT91C_PA20_RF ) |
|
|
3107
|
((unsigned int) AT91C_PA17_TD ), // Peripheral A
|
|
3108
|
0); // Peripheral B
|
|
3109
|
}
|
|
3110
|
|
|
3111
|
//*----------------------------------------------------------------------------
|
|
3112
|
//* \fn AT91F_WDTC_CfgPMC
|
|
3113
|
//* \brief Enable Peripheral clock in PMC for WDTC
|
|
3114
|
//*----------------------------------------------------------------------------
|
|
3115
|
static inline void AT91F_WDTC_CfgPMC (void)
|
|
3116
|
{
|
|
3117
|
AT91F_PMC_EnablePeriphClock(
|
|
3118
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3119
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3120
|
}
|
|
3121
|
|
|
3122
|
//*----------------------------------------------------------------------------
|
|
3123
|
//* \fn AT91F_US1_CfgPMC
|
|
3124
|
//* \brief Enable Peripheral clock in PMC for US1
|
|
3125
|
//*----------------------------------------------------------------------------
|
|
3126
|
static inline void AT91F_US1_CfgPMC (void)
|
|
3127
|
{
|
|
3128
|
AT91F_PMC_EnablePeriphClock(
|
|
3129
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3130
|
((unsigned int) 1 << AT91C_ID_US1));
|
|
3131
|
}
|
|
3132
|
|
|
3133
|
//*----------------------------------------------------------------------------
|
|
3134
|
//* \fn AT91F_US1_CfgPIO
|
|
3135
|
//* \brief Configure PIO controllers to drive US1 signals
|
|
3136
|
//*----------------------------------------------------------------------------
|
|
3137
|
static inline void AT91F_US1_CfgPIO (void)
|
|
3138
|
{
|
|
3139
|
// Configure PIO controllers to periph mode
|
|
3140
|
AT91F_PIO_CfgPeriph(
|
|
3141
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3142
|
((unsigned int) AT91C_PA29_RI1 ) |
|
|
3143
|
((unsigned int) AT91C_PA26_DCD1 ) |
|
|
3144
|
((unsigned int) AT91C_PA28_DSR1 ) |
|
|
3145
|
((unsigned int) AT91C_PA27_DTR1 ) |
|
|
3146
|
((unsigned int) AT91C_PA23_SCK1 ) |
|
|
3147
|
((unsigned int) AT91C_PA24_RTS1 ) |
|
|
3148
|
((unsigned int) AT91C_PA22_TXD1 ) |
|
|
3149
|
((unsigned int) AT91C_PA21_RXD1 ) |
|
|
3150
|
((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A
|
|
3151
|
0); // Peripheral B
|
|
3152
|
}
|
|
3153
|
|
|
3154
|
//*----------------------------------------------------------------------------
|
|
3155
|
//* \fn AT91F_US0_CfgPMC
|
|
3156
|
//* \brief Enable Peripheral clock in PMC for US0
|
|
3157
|
//*----------------------------------------------------------------------------
|
|
3158
|
static inline void AT91F_US0_CfgPMC (void)
|
|
3159
|
{
|
|
3160
|
AT91F_PMC_EnablePeriphClock(
|
|
3161
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3162
|
((unsigned int) 1 << AT91C_ID_US0));
|
|
3163
|
}
|
|
3164
|
|
|
3165
|
//*----------------------------------------------------------------------------
|
|
3166
|
//* \fn AT91F_US0_CfgPIO
|
|
3167
|
//* \brief Configure PIO controllers to drive US0 signals
|
|
3168
|
//*----------------------------------------------------------------------------
|
|
3169
|
static inline void AT91F_US0_CfgPIO (void)
|
|
3170
|
{
|
|
3171
|
// Configure PIO controllers to periph mode
|
|
3172
|
AT91F_PIO_CfgPeriph(
|
|
3173
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3174
|
((unsigned int) AT91C_PA5_RXD0 ) |
|
|
3175
|
((unsigned int) AT91C_PA8_CTS0 ) |
|
|
3176
|
((unsigned int) AT91C_PA7_RTS0 ) |
|
|
3177
|
((unsigned int) AT91C_PA6_TXD0 ), // Peripheral A
|
|
3178
|
((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B
|
|
3179
|
}
|
|
3180
|
|
|
3181
|
//*----------------------------------------------------------------------------
|
|
3182
|
//* \fn AT91F_SPI_CfgPMC
|
|
3183
|
//* \brief Enable Peripheral clock in PMC for SPI
|
|
3184
|
//*----------------------------------------------------------------------------
|
|
3185
|
static inline void AT91F_SPI_CfgPMC (void)
|
|
3186
|
{
|
|
3187
|
AT91F_PMC_EnablePeriphClock(
|
|
3188
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3189
|
((unsigned int) 1 << AT91C_ID_SPI));
|
|
3190
|
}
|
|
3191
|
|
|
3192
|
//*----------------------------------------------------------------------------
|
|
3193
|
//* \fn AT91F_SPI_CfgPIO
|
|
3194
|
//* \brief Configure PIO controllers to drive SPI signals
|
|
3195
|
//*----------------------------------------------------------------------------
|
|
3196
|
static inline void AT91F_SPI_CfgPIO (void)
|
|
3197
|
{
|
|
3198
|
// Configure PIO controllers to periph mode
|
|
3199
|
AT91F_PIO_CfgPeriph(
|
|
3200
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3201
|
((unsigned int) AT91C_PA13_MOSI ) |
|
|
3202
|
((unsigned int) AT91C_PA31_NPCS1 ) |
|
|
3203
|
((unsigned int) AT91C_PA14_SPCK ) |
|
|
3204
|
((unsigned int) AT91C_PA11_NPCS0 ) |
|
|
3205
|
((unsigned int) AT91C_PA12_MISO ), // Peripheral A
|
|
3206
|
((unsigned int) AT91C_PA9_NPCS1 ) |
|
|
3207
|
((unsigned int) AT91C_PA22_NPCS3 ) |
|
|
3208
|
((unsigned int) AT91C_PA3_NPCS3 ) |
|
|
3209
|
((unsigned int) AT91C_PA5_NPCS3 ) |
|
|
3210
|
((unsigned int) AT91C_PA10_NPCS2 ) |
|
|
3211
|
((unsigned int) AT91C_PA30_NPCS2 )); // Peripheral B
|
|
3212
|
}
|
|
3213
|
|
|
3214
|
//*----------------------------------------------------------------------------
|
|
3215
|
//* \fn AT91F_PITC_CfgPMC
|
|
3216
|
//* \brief Enable Peripheral clock in PMC for PITC
|
|
3217
|
//*----------------------------------------------------------------------------
|
|
3218
|
static inline void AT91F_PITC_CfgPMC (void)
|
|
3219
|
{
|
|
3220
|
AT91F_PMC_EnablePeriphClock(
|
|
3221
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3222
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3223
|
}
|
|
3224
|
|
|
3225
|
//*----------------------------------------------------------------------------
|
|
3226
|
//* \fn AT91F_AIC_CfgPMC
|
|
3227
|
//* \brief Enable Peripheral clock in PMC for AIC
|
|
3228
|
//*----------------------------------------------------------------------------
|
|
3229
|
static inline void AT91F_AIC_CfgPMC (void)
|
|
3230
|
{
|
|
3231
|
AT91F_PMC_EnablePeriphClock(
|
|
3232
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3233
|
((unsigned int) 1 << AT91C_ID_FIQ) |
|
|
3234
|
((unsigned int) 1 << AT91C_ID_IRQ0) |
|
|
3235
|
((unsigned int) 1 << AT91C_ID_IRQ1));
|
|
3236
|
}
|
|
3237
|
|
|
3238
|
//*----------------------------------------------------------------------------
|
|
3239
|
//* \fn AT91F_AIC_CfgPIO
|
|
3240
|
//* \brief Configure PIO controllers to drive AIC signals
|
|
3241
|
//*----------------------------------------------------------------------------
|
|
3242
|
static inline void AT91F_AIC_CfgPIO (void)
|
|
3243
|
{
|
|
3244
|
// Configure PIO controllers to periph mode
|
|
3245
|
AT91F_PIO_CfgPeriph(
|
|
3246
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3247
|
((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A
|
|
3248
|
((unsigned int) AT91C_PA20_IRQ0 ) |
|
|
3249
|
((unsigned int) AT91C_PA19_FIQ )); // Peripheral B
|
|
3250
|
}
|
|
3251
|
|
|
3252
|
//*----------------------------------------------------------------------------
|
|
3253
|
//* \fn AT91F_TWI_CfgPMC
|
|
3254
|
//* \brief Enable Peripheral clock in PMC for TWI
|
|
3255
|
//*----------------------------------------------------------------------------
|
|
3256
|
static inline void AT91F_TWI_CfgPMC (void)
|
|
3257
|
{
|
|
3258
|
AT91F_PMC_EnablePeriphClock(
|
|
3259
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3260
|
((unsigned int) 1 << AT91C_ID_TWI));
|
|
3261
|
}
|
|
3262
|
|
|
3263
|
//*----------------------------------------------------------------------------
|
|
3264
|
//* \fn AT91F_TWI_CfgPIO
|
|
3265
|
//* \brief Configure PIO controllers to drive TWI signals
|
|
3266
|
//*----------------------------------------------------------------------------
|
|
3267
|
static inline void AT91F_TWI_CfgPIO (void)
|
|
3268
|
{
|
|
3269
|
// Configure PIO controllers to periph mode
|
|
3270
|
AT91F_PIO_CfgPeriph(
|
|
3271
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3272
|
((unsigned int) AT91C_PA4_TWCK ) |
|
|
3273
|
((unsigned int) AT91C_PA3_TWD ), // Peripheral A
|
|
3274
|
0); // Peripheral B
|
|
3275
|
}
|
|
3276
|
|
|
3277
|
//*----------------------------------------------------------------------------
|
|
3278
|
//* \fn AT91F_PWMC_CH3_CfgPIO
|
|
3279
|
//* \brief Configure PIO controllers to drive PWMC_CH3 signals
|
|
3280
|
//*----------------------------------------------------------------------------
|
|
3281
|
static inline void AT91F_PWMC_CH3_CfgPIO (void)
|
|
3282
|
{
|
|
3283
|
// Configure PIO controllers to periph mode
|
|
3284
|
AT91F_PIO_CfgPeriph(
|
|
3285
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3286
|
0, // Peripheral A
|
|
3287
|
((unsigned int) AT91C_PA7_PWM3 ) |
|
|
3288
|
((unsigned int) AT91C_PA14_PWM3 )); // Peripheral B
|
|
3289
|
}
|
|
3290
|
|
|
3291
|
//*----------------------------------------------------------------------------
|
|
3292
|
//* \fn AT91F_PWMC_CH2_CfgPIO
|
|
3293
|
//* \brief Configure PIO controllers to drive PWMC_CH2 signals
|
|
3294
|
//*----------------------------------------------------------------------------
|
|
3295
|
static inline void AT91F_PWMC_CH2_CfgPIO (void)
|
|
3296
|
{
|
|
3297
|
// Configure PIO controllers to periph mode
|
|
3298
|
AT91F_PIO_CfgPeriph(
|
|
3299
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3300
|
((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A
|
|
3301
|
((unsigned int) AT91C_PA13_PWM2 ) |
|
|
3302
|
((unsigned int) AT91C_PA25_PWM2 )); // Peripheral B
|
|
3303
|
}
|
|
3304
|
|
|
3305
|
//*----------------------------------------------------------------------------
|
|
3306
|
//* \fn AT91F_PWMC_CH1_CfgPIO
|
|
3307
|
//* \brief Configure PIO controllers to drive PWMC_CH1 signals
|
|
3308
|
//*----------------------------------------------------------------------------
|
|
3309
|
static inline void AT91F_PWMC_CH1_CfgPIO (void)
|
|
3310
|
{
|
|
3311
|
// Configure PIO controllers to periph mode
|
|
3312
|
AT91F_PIO_CfgPeriph(
|
|
3313
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3314
|
((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A
|
|
3315
|
((unsigned int) AT91C_PA24_PWM1 ) |
|
|
3316
|
((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B
|
|
3317
|
}
|
|
3318
|
|
|
3319
|
//*----------------------------------------------------------------------------
|
|
3320
|
//* \fn AT91F_PWMC_CH0_CfgPIO
|
|
3321
|
//* \brief Configure PIO controllers to drive PWMC_CH0 signals
|
|
3322
|
//*----------------------------------------------------------------------------
|
|
3323
|
static inline void AT91F_PWMC_CH0_CfgPIO (void)
|
|
3324
|
{
|
|
3325
|
// Configure PIO controllers to periph mode
|
|
3326
|
AT91F_PIO_CfgPeriph(
|
|
3327
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3328
|
((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A
|
|
3329
|
((unsigned int) AT91C_PA23_PWM0 ) |
|
|
3330
|
((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B
|
|
3331
|
}
|
|
3332
|
|
|
3333
|
//*----------------------------------------------------------------------------
|
|
3334
|
//* \fn AT91F_ADC_CfgPMC
|
|
3335
|
//* \brief Enable Peripheral clock in PMC for ADC
|
|
3336
|
//*----------------------------------------------------------------------------
|
|
3337
|
static inline void AT91F_ADC_CfgPMC (void)
|
|
3338
|
{
|
|
3339
|
AT91F_PMC_EnablePeriphClock(
|
|
3340
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3341
|
((unsigned int) 1 << AT91C_ID_ADC));
|
|
3342
|
}
|
|
3343
|
|
|
3344
|
//*----------------------------------------------------------------------------
|
|
3345
|
//* \fn AT91F_ADC_CfgPIO
|
|
3346
|
//* \brief Configure PIO controllers to drive ADC signals
|
|
3347
|
//*----------------------------------------------------------------------------
|
|
3348
|
static inline void AT91F_ADC_CfgPIO (void)
|
|
3349
|
{
|
|
3350
|
// Configure PIO controllers to periph mode
|
|
3351
|
AT91F_PIO_CfgPeriph(
|
|
3352
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3353
|
0, // Peripheral A
|
|
3354
|
((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B
|
|
3355
|
}
|
|
3356
|
|
|
3357
|
//*----------------------------------------------------------------------------
|
|
3358
|
//* \fn AT91F_RTTC_CfgPMC
|
|
3359
|
//* \brief Enable Peripheral clock in PMC for RTTC
|
|
3360
|
//*----------------------------------------------------------------------------
|
|
3361
|
static inline void AT91F_RTTC_CfgPMC (void)
|
|
3362
|
{
|
|
3363
|
AT91F_PMC_EnablePeriphClock(
|
|
3364
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3365
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3366
|
}
|
|
3367
|
|
|
3368
|
//*----------------------------------------------------------------------------
|
|
3369
|
//* \fn AT91F_UDP_CfgPMC
|
|
3370
|
//* \brief Enable Peripheral clock in PMC for UDP
|
|
3371
|
//*----------------------------------------------------------------------------
|
|
3372
|
static inline void AT91F_UDP_CfgPMC (void)
|
|
3373
|
{
|
|
3374
|
AT91F_PMC_EnablePeriphClock(
|
|
3375
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3376
|
((unsigned int) 1 << AT91C_ID_UDP));
|
|
3377
|
}
|
|
3378
|
|
|
3379
|
//*----------------------------------------------------------------------------
|
|
3380
|
//* \fn AT91F_TC0_CfgPMC
|
|
3381
|
//* \brief Enable Peripheral clock in PMC for TC0
|
|
3382
|
//*----------------------------------------------------------------------------
|
|
3383
|
static inline void AT91F_TC0_CfgPMC (void)
|
|
3384
|
{
|
|
3385
|
AT91F_PMC_EnablePeriphClock(
|
|
3386
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3387
|
((unsigned int) 1 << AT91C_ID_TC0));
|
|
3388
|
}
|
|
3389
|
|
|
3390
|
//*----------------------------------------------------------------------------
|
|
3391
|
//* \fn AT91F_TC0_CfgPIO
|
|
3392
|
//* \brief Configure PIO controllers to drive TC0 signals
|
|
3393
|
//*----------------------------------------------------------------------------
|
|
3394
|
static inline void AT91F_TC0_CfgPIO (void)
|
|
3395
|
{
|
|
3396
|
// Configure PIO controllers to periph mode
|
|
3397
|
AT91F_PIO_CfgPeriph(
|
|
3398
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3399
|
0, // Peripheral A
|
|
3400
|
((unsigned int) AT91C_PA0_TIOA0 ) |
|
|
3401
|
((unsigned int) AT91C_PA4_TCLK0 ) |
|
|
3402
|
((unsigned int) AT91C_PA1_TIOB0 )); // Peripheral B
|
|
3403
|
}
|
|
3404
|
|
|
3405
|
//*----------------------------------------------------------------------------
|
|
3406
|
//* \fn AT91F_TC1_CfgPMC
|
|
3407
|
//* \brief Enable Peripheral clock in PMC for TC1
|
|
3408
|
//*----------------------------------------------------------------------------
|
|
3409
|
static inline void AT91F_TC1_CfgPMC (void)
|
|
3410
|
{
|
|
3411
|
AT91F_PMC_EnablePeriphClock(
|
|
3412
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3413
|
((unsigned int) 1 << AT91C_ID_TC1));
|
|
3414
|
}
|
|
3415
|
|
|
3416
|
//*----------------------------------------------------------------------------
|
|
3417
|
//* \fn AT91F_TC1_CfgPIO
|
|
3418
|
//* \brief Configure PIO controllers to drive TC1 signals
|
|
3419
|
//*----------------------------------------------------------------------------
|
|
3420
|
static inline void AT91F_TC1_CfgPIO (void)
|
|
3421
|
{
|
|
3422
|
// Configure PIO controllers to periph mode
|
|
3423
|
AT91F_PIO_CfgPeriph(
|
|
3424
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3425
|
0, // Peripheral A
|
|
3426
|
((unsigned int) AT91C_PA15_TIOA1 ) |
|
|
3427
|
((unsigned int) AT91C_PA28_TCLK1 ) |
|
|
3428
|
((unsigned int) AT91C_PA16_TIOB1 )); // Peripheral B
|
|
3429
|
}
|
|
3430
|
|
|
3431
|
//*----------------------------------------------------------------------------
|
|
3432
|
//* \fn AT91F_TC2_CfgPMC
|
|
3433
|
//* \brief Enable Peripheral clock in PMC for TC2
|
|
3434
|
//*----------------------------------------------------------------------------
|
|
3435
|
static inline void AT91F_TC2_CfgPMC (void)
|
|
3436
|
{
|
|
3437
|
AT91F_PMC_EnablePeriphClock(
|
|
3438
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3439
|
((unsigned int) 1 << AT91C_ID_TC2));
|
|
3440
|
}
|
|
3441
|
|
|
3442
|
//*----------------------------------------------------------------------------
|
|
3443
|
//* \fn AT91F_TC2_CfgPIO
|
|
3444
|
//* \brief Configure PIO controllers to drive TC2 signals
|
|
3445
|
//*----------------------------------------------------------------------------
|
|
3446
|
static inline void AT91F_TC2_CfgPIO (void)
|
|
3447
|
{
|
|
3448
|
// Configure PIO controllers to periph mode
|
|
3449
|
AT91F_PIO_CfgPeriph(
|
|
3450
|
AT91C_BASE_PIOA, // PIO controller base address
|
|
3451
|
0, // Peripheral A
|
|
3452
|
((unsigned int) AT91C_PA27_TIOB2 ) |
|
|
3453
|
((unsigned int) AT91C_PA26_TIOA2 ) |
|
|
3454
|
((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B
|
|
3455
|
}
|
|
3456
|
|
|
3457
|
//*----------------------------------------------------------------------------
|
|
3458
|
//* \fn AT91F_MC_CfgPMC
|
|
3459
|
//* \brief Enable Peripheral clock in PMC for MC
|
|
3460
|
//*----------------------------------------------------------------------------
|
|
3461
|
static inline void AT91F_MC_CfgPMC (void)
|
|
3462
|
{
|
|
3463
|
AT91F_PMC_EnablePeriphClock(
|
|
3464
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3465
|
((unsigned int) 1 << AT91C_ID_SYS));
|
|
3466
|
}
|
|
3467
|
|
|
3468
|
//*----------------------------------------------------------------------------
|
|
3469
|
//* \fn AT91F_PIOA_CfgPMC
|
|
3470
|
//* \brief Enable Peripheral clock in PMC for PIOA
|
|
3471
|
//*----------------------------------------------------------------------------
|
|
3472
|
static inline void AT91F_PIOA_CfgPMC (void)
|
|
3473
|
{
|
|
3474
|
AT91F_PMC_EnablePeriphClock(
|
|
3475
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3476
|
((unsigned int) 1 << AT91C_ID_PIOA));
|
|
3477
|
}
|
|
3478
|
|
|
3479
|
//*----------------------------------------------------------------------------
|
|
3480
|
//* \fn AT91F_PWMC_CfgPMC
|
|
3481
|
//* \brief Enable Peripheral clock in PMC for PWMC
|
|
3482
|
//*----------------------------------------------------------------------------
|
|
3483
|
static inline void AT91F_PWMC_CfgPMC (void)
|
|
3484
|
{
|
|
3485
|
AT91F_PMC_EnablePeriphClock(
|
|
3486
|
AT91C_BASE_PMC, // PIO controller base address
|
|
3487
|
((unsigned int) 1 << AT91C_ID_PWMC));
|
|
3488
|
}
|
|
3489
|
|
|
3490
|
#define __ramfunc __attribute__ ((long_call, section (".fastrun")))
|
|
3491
|
|
|
3492
|
#endif // lib_AT91SAM7S64_H
|
