|
1
|
/*
|
|
2
|
* linux/include/asm-arm/ptrace.h
|
|
3
|
*
|
|
4
|
* Copyright (C) 1996-2003 Russell King
|
|
5
|
*
|
|
6
|
* This program is free software; you can redistribute it and/or modify
|
|
7
|
* it under the terms of the GNU General Public License version 2 as
|
|
8
|
* published by the Free Software Foundation.
|
|
9
|
*/
|
|
10
|
#ifndef __ASM_ARM_PTRACE_H
|
|
11
|
#define __ASM_ARM_PTRACE_H
|
|
12
|
|
|
13
|
/*
|
|
14
|
* PSR bits
|
|
15
|
*/
|
|
16
|
#define USR26_MODE 0x00000000
|
|
17
|
#define FIQ26_MODE 0x00000001
|
|
18
|
#define IRQ26_MODE 0x00000002
|
|
19
|
#define SVC26_MODE 0x00000003
|
|
20
|
#define USR_MODE 0x00000010
|
|
21
|
#define FIQ_MODE 0x00000011
|
|
22
|
#define IRQ_MODE 0x00000012
|
|
23
|
#define SVC_MODE 0x00000013
|
|
24
|
#define ABT_MODE 0x00000017
|
|
25
|
#define UND_MODE 0x0000001b
|
|
26
|
#define SYSTEM_MODE 0x0000001f
|
|
27
|
#define MODE32_BIT 0x00000010
|
|
28
|
#define MODE_MASK 0x0000001f
|
|
29
|
#define PSR_T_BIT 0x00000020
|
|
30
|
#define PSR_F_BIT 0x00000040
|
|
31
|
#define PSR_I_BIT 0x00000080
|
|
32
|
#define PSR_J_BIT 0x01000000
|
|
33
|
#define PSR_Q_BIT 0x08000000
|
|
34
|
#define PSR_V_BIT 0x10000000
|
|
35
|
#define PSR_C_BIT 0x20000000
|
|
36
|
#define PSR_Z_BIT 0x40000000
|
|
37
|
#define PSR_N_BIT 0x80000000
|
|
38
|
#define PCMASK 0
|
|
39
|
|
|
40
|
/*
|
|
41
|
* Groups of PSR bits
|
|
42
|
*/
|
|
43
|
#define PSR_f 0xff000000 /* Flags */
|
|
44
|
#define PSR_s 0x00ff0000 /* Status */
|
|
45
|
#define PSR_x 0x0000ff00 /* Extension */
|
|
46
|
#define PSR_c 0x000000ff /* Control */
|
|
47
|
|
|
48
|
#ifndef __ASSEMBLY__
|
|
49
|
|
|
50
|
/*
|
|
51
|
* This struct defines the way the registers are stored on the
|
|
52
|
* stack during a system call. Note that sizeof(struct pt_regs)
|
|
53
|
* has to be a multiple of 8.
|
|
54
|
*/
|
|
55
|
struct pt_regs {
|
|
56
|
long uregs[18];
|
|
57
|
};
|
|
58
|
|
|
59
|
#define ARM_cpsr uregs[16]
|
|
60
|
#define ARM_pc uregs[15]
|
|
61
|
#define ARM_lr uregs[14]
|
|
62
|
#define ARM_sp uregs[13]
|
|
63
|
#define ARM_ip uregs[12]
|
|
64
|
#define ARM_fp uregs[11]
|
|
65
|
#define ARM_r10 uregs[10]
|
|
66
|
#define ARM_r9 uregs[9]
|
|
67
|
#define ARM_r8 uregs[8]
|
|
68
|
#define ARM_r7 uregs[7]
|
|
69
|
#define ARM_r6 uregs[6]
|
|
70
|
#define ARM_r5 uregs[5]
|
|
71
|
#define ARM_r4 uregs[4]
|
|
72
|
#define ARM_r3 uregs[3]
|
|
73
|
#define ARM_r2 uregs[2]
|
|
74
|
#define ARM_r1 uregs[1]
|
|
75
|
#define ARM_r0 uregs[0]
|
|
76
|
#define ARM_ORIG_r0 uregs[17]
|
|
77
|
|
|
78
|
#define user_mode(regs) \
|
|
79
|
(((regs)->ARM_cpsr & 0xf) == 0)
|
|
80
|
|
|
81
|
#ifdef CONFIG_ARM_THUMB
|
|
82
|
#define thumb_mode(regs) \
|
|
83
|
(((regs)->ARM_cpsr & PSR_T_BIT))
|
|
84
|
#else
|
|
85
|
#define thumb_mode(regs) (0)
|
|
86
|
#endif
|
|
87
|
|
|
88
|
#define processor_mode(regs) \
|
|
89
|
((regs)->ARM_cpsr & MODE_MASK)
|
|
90
|
|
|
91
|
#define interrupts_enabled(regs) \
|
|
92
|
(!((regs)->ARM_cpsr & PSR_I_BIT))
|
|
93
|
|
|
94
|
#define fast_interrupts_enabled(regs) \
|
|
95
|
(!((regs)->ARM_cpsr & PSR_F_BIT))
|
|
96
|
|
|
97
|
#define condition_codes(regs) \
|
|
98
|
((regs)->ARM_cpsr & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT))
|
|
99
|
|
|
100
|
/* Are the current registers suitable for user mode?
|
|
101
|
* (used to maintain security in signal handlers)
|
|
102
|
*/
|
|
103
|
static inline int valid_user_regs(struct pt_regs *regs)
|
|
104
|
{
|
|
105
|
if (user_mode(regs) &&
|
|
106
|
(regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0)
|
|
107
|
return 1;
|
|
108
|
|
|
109
|
/*
|
|
110
|
* Force CPSR to something logical...
|
|
111
|
*/
|
|
112
|
regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
|
|
113
|
|
|
114
|
return 0;
|
|
115
|
}
|
|
116
|
|
|
117
|
#define pc_pointer(v) \
|
|
118
|
((v) & ~PCMASK)
|
|
119
|
|
|
120
|
#define instruction_pointer(regs) \
|
|
121
|
(pc_pointer((regs)->ARM_pc))
|
|
122
|
|
|
123
|
#define profile_pc(regs) instruction_pointer(regs)
|
|
124
|
|
|
125
|
#endif /* __ASSEMBLY__ */
|
|
126
|
|
|
127
|
#endif
|
|
128
|
|
