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1
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PICCSIM design
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2
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3
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ISO14443 anticollision:
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4
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- Configure TC
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5
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- to reset TC2 on every falling edge
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6
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- to use FORCE_FAST for TC IRQ
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7
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- to enable TC2 ETRGS
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8
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- CARRIER_DIV is switched to 212kHz / 424kHz
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9
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- this results in SSC Rx is 4x (2x?) oversampling
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10
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- Set SSC Rx start condition to 4x/2x SOF pattern
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11
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- upon reception of first falling edge, we
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12
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- end up in TC FIQ
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13
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- read out TC0 current value
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14
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- reconfigure TC0 RA/RB to be in-phase with previously-read TC0
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15
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value (subtracting some fixed offset depending on FIQ latency)
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16
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- reconfigure TC2
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17
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- to use external event on every rising edge
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18
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- to reset(trigger) on every external event
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19
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- to clear TIOA2 on RC compare (RC is high)
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20
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- to set TIOA2 on RA compare (RA set later)
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21
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- disable TC2 IRQ (and FIQ FAST_FORCE)
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22
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- Wait for SSC Rx Interrupt (DMA complete, or PIO)
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23
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- Read and decode single 32bit word
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24
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- determine whether it is REQA or WUPA
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25
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- abort if not, start over
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26
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- depending on last bit 0/1, configure TC2 RA (FDT)
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27
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- recconfig TC0 to produce 1.6MHz CARRIER_DIV clock for SSC Tx
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28
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- make sure this is done synchronously
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29
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-
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30
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- set up SSC Tx
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31
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- DMA with pre-encoded (and user-configured) ATQA
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32
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- start Tx at a rising edge of TF (asserted by TC2 RA)
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33
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- Send Interrupt once TX DMA is done
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34
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- Once TC2 RA compare happens, the rising edge of TIOA2 will trigger SSC
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35
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- Wait for SSC Tx DMA to finish
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36
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- Repeat similar steps for ANTICOL/SELECT command, differences:
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37
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- single-byte compare after frame Rx is not sufficient
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38
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- evaluate number of valid bits ASAP
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39
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- we might receive and transmit split frame at non-byte-boundaries
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40
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- just shift a prepared ANTICOL/Select response
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41
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- make sure parity is handled correctly!
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42
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- Once we've completed the select, we go on with normal
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