/openpicc/os/core/ARM7_AT91SAM7S/lib_AT91SAM7.h - Annotate - SIMtrace - Open Source Mobile Communications

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henryk

//* ----------------------------------------------------------------------------

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//*         ATMEL Microcontroller Software Support  -  ROUSSET  -

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//* ----------------------------------------------------------------------------

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//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR

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//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

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//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE

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//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,

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//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

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//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

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//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

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//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

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//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,

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//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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//* ----------------------------------------------------------------------------

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//* File Name           : lib_AT91SAM7S64.h

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//* Object              : AT91SAM7S64 inlined functions

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//* Generated           : AT91 SW Application Group  08/30/2005 (15:52:59)

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//*

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//* CVS Reference       : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005//

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//* CVS Reference       : /lib_pmc_SAM7S.h/1.4/Tue Aug 30 13:00:43 2005//

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//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//

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//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//

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//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//

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//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//

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//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//

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//* CVS Reference       : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005//

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//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//

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//* CVS Reference       : /lib_aic_6075b.h/1.2/Thu Jul  7 07:48:22 2005//

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//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//

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//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//

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//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//

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//* CVS Reference       : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005//

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//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//

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//* CVS Reference       : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004//

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//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//

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//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//

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//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//

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//* ----------------------------------------------------------------------------

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#ifndef lib_AT91SAM7_H

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#define lib_AT91SAM7_H

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#include <AT91SAM7.h>

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typedef void (*THandler) (void);

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/* *****************************************************************************

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                SOFTWARE API FOR AIC

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   ***************************************************************************** */

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#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20)	// ldr, pc, [pc, #-&F20]

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_ConfigureIt

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//* \brief Interrupt Handler Initialization

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//*----------------------------------------------------------------------------

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extern unsigned int AT91F_AIC_ConfigureIt (unsigned int irq_id,	// \arg interrupt number to initialize

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					   unsigned int priority,	// \arg priority to give to the interrupt

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					   unsigned int src_type,	// \arg activation and sense of activation

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					   THandler handler);	// \arg address of the interrupt handler

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_EnableIt

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//* \brief Enable corresponding IT number

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_AIC_EnableIt (unsigned int irq_id)	// \arg interrupt number to initialize

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  //* Enable the interrupt on the interrupt controller

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  AT91C_BASE_AIC->AIC_IECR = 0x1 << irq_id;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_DisableIt

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//* \brief Disable corresponding IT number

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_AIC_DisableIt (unsigned int irq_id)	// \arg interrupt number to initialize

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  unsigned int mask = 0x1 << irq_id;

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  //* Disable the interrupt on the interrupt controller

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  AT91C_BASE_AIC->AIC_IDCR = mask;

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  //* Clear the interrupt on the Interrupt Controller ( if one is pending )

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  AT91C_BASE_AIC->AIC_ICCR = mask;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_ClearIt

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//* \brief Clear corresponding IT number

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_AIC_ClearIt (unsigned int irq_id)	// \arg interrupt number to initialize

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  //* Clear the interrupt on the Interrupt Controller ( if one is pending )

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  AT91C_BASE_AIC->AIC_ICCR = (0x1 << irq_id);

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_AcknowledgeIt

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//* \brief Acknowledge corresponding IT number

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_AIC_AcknowledgeIt (void)

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  AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_AIC->AIC_EOICR;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_SetExceptionVector

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//* \brief Configure vector handler

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//*----------------------------------------------------------------------------

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extern unsigned int AT91F_AIC_SetExceptionVector (unsigned int *pVector,	// \arg pointer to the AIC registers

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						  THandler Handler);	// \arg Interrupt Handler

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_Trig

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//* \brief Trig an IT

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_AIC_Trig (AT91PS_AIC pAic,	// \arg pointer to the AIC registers

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		unsigned int irq_id)	// \arg interrupt number

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  pAic->AIC_ISCR = (0x1 << irq_id);

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_IsActive

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//* \brief Test if an IT is active

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//*----------------------------------------------------------------------------

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static inline unsigned int

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AT91F_AIC_IsActive (AT91PS_AIC pAic,	// \arg pointer to the AIC registers

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		    unsigned int irq_id)	// \arg Interrupt Number

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  return (pAic->AIC_ISR & (0x1 << irq_id));

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_IsPending

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//* \brief Test if an IT is pending

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//*----------------------------------------------------------------------------

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static inline unsigned int

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AT91F_AIC_IsPending (AT91PS_AIC pAic,	// \arg pointer to the AIC registers

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		     unsigned int irq_id)	// \arg Interrupt Number

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  return (pAic->AIC_IPR & (0x1 << irq_id));

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_AIC_Open

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//* \brief Set exception vectors and AIC registers to default values

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//*----------------------------------------------------------------------------

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extern void AT91F_AIC_Open (THandler IrqHandler,	// \arg Default IRQ vector exception

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			    THandler FiqHandler,	// \arg Default FIQ vector exception

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			    THandler DefaultHandler,	// \arg Default Handler set in ISR

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			    THandler SpuriousHandler,	// \arg Default Spurious Handler

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			    unsigned int protectMode);	// \arg Debug Control Register

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/* *****************************************************************************

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                SOFTWARE API FOR PDC

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   ***************************************************************************** */

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_SetNextRx

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//* \brief Set the next receive transfer descriptor

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_SetNextRx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller

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		     unsigned char *address,	// \arg address to the next bloc to be received

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		     unsigned int bytes)	// \arg number of bytes to be received

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  pPDC->PDC_RNPR = (unsigned int) address;

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  pPDC->PDC_RNCR = bytes;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_SetNextTx

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//* \brief Set the next transmit transfer descriptor

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_SetNextTx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller

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		     const unsigned char *address,	// \arg address to the next bloc to be transmitted

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		     unsigned int bytes)	// \arg number of bytes to be transmitted

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  pPDC->PDC_TNPR = (unsigned int) address;

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  pPDC->PDC_TNCR = bytes;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_SetRx

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//* \brief Set the receive transfer descriptor

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_SetRx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller

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		 unsigned char *address,	// \arg address to the next bloc to be received

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		 unsigned int bytes)	// \arg number of bytes to be received

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  pPDC->PDC_RPR = (unsigned int) address;

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  pPDC->PDC_RCR = bytes;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_SetTx

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//* \brief Set the transmit transfer descriptor

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_SetTx (AT91PS_PDC pPDC,	// \arg pointer to a PDC controller

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		 const unsigned char *address,	// \arg address to the next bloc to be transmitted

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		 unsigned int bytes)	// \arg number of bytes to be transmitted

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  pPDC->PDC_TPR = (unsigned int) address;

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  pPDC->PDC_TCR = bytes;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_EnableTx

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//* \brief Enable transmit

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_EnableTx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  pPDC->PDC_PTCR = AT91C_PDC_TXTEN;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_EnableRx

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//* \brief Enable receive

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_EnableRx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  pPDC->PDC_PTCR = AT91C_PDC_RXTEN;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_DisableTx

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//* \brief Disable transmit

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_DisableTx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_DisableRx

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//* \brief Disable receive

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PDC_DisableRx (AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_IsTxEmpty

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//* \brief Test if the current transfer descriptor has been sent

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//*----------------------------------------------------------------------------

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static inline int

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AT91F_PDC_IsTxEmpty (		// \return return 1 if transfer is complete

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		      AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  return !(pPDC->PDC_TCR);

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_IsNextTxEmpty

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//* \brief Test if the next transfer descriptor has been moved to the current td

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//*----------------------------------------------------------------------------

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static inline int

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AT91F_PDC_IsNextTxEmpty (	// \return return 1 if transfer is complete

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			  AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  return !(pPDC->PDC_TNCR);

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_IsRxEmpty

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//* \brief Test if the current transfer descriptor has been filled

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//*----------------------------------------------------------------------------

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static inline int

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AT91F_PDC_IsRxEmpty (		// \return return 1 if transfer is complete

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		      AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  return !(pPDC->PDC_RCR);

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_IsNextRxEmpty

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//* \brief Test if the next transfer descriptor has been moved to the current td

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//*----------------------------------------------------------------------------

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static inline int

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AT91F_PDC_IsNextRxEmpty (	// \return return 1 if transfer is complete

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			  AT91PS_PDC pPDC)	// \arg pointer to a PDC controller

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  return !(pPDC->PDC_RNCR);

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_Open

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//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX

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//*----------------------------------------------------------------------------

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extern void AT91F_PDC_Open (AT91PS_PDC pPDC);	// \arg pointer to a PDC controller

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_Close

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//* \brief Close PDC: disable TX and RX reset transfer descriptors

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//*----------------------------------------------------------------------------

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extern void AT91F_PDC_Close (AT91PS_PDC pPDC);	// \arg pointer to a PDC controller

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_SendFrame

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//* \brief Close PDC: disable TX and RX reset transfer descriptors

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//*----------------------------------------------------------------------------

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extern unsigned int AT91F_PDC_SendFrame (AT91PS_PDC pPDC,

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					 const unsigned char *pBuffer,

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					 unsigned int szBuffer,

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					 const unsigned char *pNextBuffer,

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					 unsigned int szNextBuffer);

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PDC_ReceiveFrame

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//* \brief Close PDC: disable TX and RX reset transfer descriptors

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//*----------------------------------------------------------------------------

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extern unsigned int AT91F_PDC_ReceiveFrame (AT91PS_PDC pPDC,

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					    unsigned char *pBuffer,

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					    unsigned int szBuffer,

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					    unsigned char *pNextBuffer,

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					    unsigned int szNextBuffer);

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/* *****************************************************************************

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                SOFTWARE API FOR DBGU

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   ***************************************************************************** */

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_DBGU_InterruptEnable

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//* \brief Enable DBGU Interrupt

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_DBGU_InterruptEnable (AT91PS_DBGU pDbgu,	// \arg  pointer to a DBGU controller

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			    unsigned int flag)	// \arg  dbgu interrupt to be enabled

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  pDbgu->DBGU_IER = flag;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_DBGU_InterruptDisable

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//* \brief Disable DBGU Interrupt

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_DBGU_InterruptDisable (AT91PS_DBGU pDbgu,	// \arg  pointer to a DBGU controller

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			     unsigned int flag)	// \arg  dbgu interrupt to be disabled

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  pDbgu->DBGU_IDR = flag;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_DBGU_GetInterruptMaskStatus

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//* \brief Return DBGU Interrupt Mask Status

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//*----------------------------------------------------------------------------

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static inline unsigned int

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AT91F_DBGU_GetInterruptMaskStatus (	// \return DBGU Interrupt Mask Status

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				    AT91PS_DBGU pDbgu)	// \arg  pointer to a DBGU controller

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  return pDbgu->DBGU_IMR;

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_DBGU_IsInterruptMasked

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//* \brief Test if DBGU Interrupt is Masked

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//*----------------------------------------------------------------------------

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static inline int

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AT91F_DBGU_IsInterruptMasked (AT91PS_DBGU pDbgu,	// \arg  pointer to a DBGU controller

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			      unsigned int flag)	// \arg  flag to be tested

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  return (AT91F_DBGU_GetInterruptMaskStatus (pDbgu) & flag);

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/* *****************************************************************************

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                SOFTWARE API FOR PIO

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   ***************************************************************************** */

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PIO_CfgPeriph

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//* \brief Enable pins to be drived by peripheral

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PIO_CfgPeriph (AT91PS_PIO pPio,	// \arg pointer to a PIO controller

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		     unsigned int periphAEnable,	// \arg PERIPH A to enable

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		     unsigned int periphBEnable)	// \arg PERIPH B to enable

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  pPio->PIO_ASR = periphAEnable;

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  pPio->PIO_BSR = periphBEnable;

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  pPio->PIO_PDR = (periphAEnable | periphBEnable);	// Set in Periph mode

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//*----------------------------------------------------------------------------

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//* \fn    AT91F_PIO_CfgOutput

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//* \brief Enable PIO in output mode

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//*----------------------------------------------------------------------------

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static inline void

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AT91F_PIO_CfgOutput (AT91PS_PIO pPio,	// \arg pointer to a PIO controller

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		     unsigned int pioEnable)	// \arg PIO to be enabled

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400

  pPio->PIO_PER = pioEnable;	// Set in PIO mode

401

  pPio->PIO_OER = pioEnable;	// Configure in Output

402

403

404

//*----------------------------------------------------------------------------

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//* \fn    AT91F_PIO_CfgInput

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//* \brief Enable PIO in input mode

407

//*----------------------------------------------------------------------------

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static inline void

409

AT91F_PIO_CfgInput (AT91PS_PIO pPio,	// \arg pointer to a PIO controller

410

		    unsigned int inputEnable)	// \arg PIO to be enabled

411

412

  // Disable output

413

  pPio->PIO_ODR = inputEnable;

414

  pPio->PIO_PER = inputEnable;

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417

//*----------------------------------------------------------------------------

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//* \fn    AT91F_PIO_CfgOpendrain

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//* \brief Configure PIO in open drain

420

//*----------------------------------------------------------------------------

421

static inline void

422

AT91F_PIO_CfgOpendrain (AT91PS_PIO pPio,	// \arg pointer to a PIO controller

423

			unsigned int multiDrvEnable)	// \arg pio to be configured in open drain

424

425

  // Configure the multi-drive option

426

  pPio->PIO_MDDR = ~multiDrvEnable;

427

  pPio->PIO_MDER = multiDrvEnable;

428

429

430

//*----------------------------------------------------------------------------

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//* \fn    AT91F_PIO_CfgPullup

432

//* \brief Enable pullup on PIO

433

//*----------------------------------------------------------------------------

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static inline void

435

AT91F_PIO_CfgPullup (AT91PS_PIO pPio,	// \arg pointer to a PIO controller

436

		     unsigned int pullupEnable)	// \arg enable pullup on PIO

437

438

  // Connect or not Pullup

439

  pPio->PIO_PPUDR = ~pullupEnable;

440

  pPio->PIO_PPUER = pullupEnable;

441

442

443

//*----------------------------------------------------------------------------

444

//* \fn    AT91F_PIO_CfgDirectDrive

445

//* \brief Enable direct drive on PIO

446

//*----------------------------------------------------------------------------

447

static inline void

448

AT91F_PIO_CfgDirectDrive (AT91PS_PIO pPio,	// \arg pointer to a PIO controller

449

			  unsigned int directDrive)	// \arg PIO to be configured with direct drive

450

451

  // Configure the Direct Drive

452

  pPio->PIO_OWDR = ~directDrive;

453

  pPio->PIO_OWER = directDrive;

454

455

456

//*----------------------------------------------------------------------------

457

//* \fn    AT91F_PIO_CfgInputFilter

458

//* \brief Enable input filter on input PIO

459

//*----------------------------------------------------------------------------

460

static inline void

461

AT91F_PIO_CfgInputFilter (AT91PS_PIO pPio,	// \arg pointer to a PIO controller

462

			  unsigned int inputFilter)	// \arg PIO to be configured with input filter

463

464

  // Configure the Direct Drive

465

  pPio->PIO_IFDR = ~inputFilter;

466

  pPio->PIO_IFER = inputFilter;

467

468

469

//*----------------------------------------------------------------------------

470

//* \fn    AT91F_PIO_GetInput

471

//* \brief Return PIO input value

472

//*----------------------------------------------------------------------------

473

static inline unsigned int

474

AT91F_PIO_GetInput (		// \return PIO input

475

		     AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

476

477

  return pPio->PIO_PDSR;

478

479

480

//*----------------------------------------------------------------------------

481

//* \fn    AT91F_PIO_IsInputSet

482

//* \brief Test if PIO is input flag is active

483

//*----------------------------------------------------------------------------

484

static inline int

485

AT91F_PIO_IsInputSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

486

		      unsigned int flag)	// \arg  flag to be tested

487

488

  return (AT91F_PIO_GetInput (pPio) & flag);

//*----------------------------------------------------------------------------

493

//* \fn    AT91F_PIO_SetOutput

494

//* \brief Set to 1 output PIO

495

//*----------------------------------------------------------------------------

496

static inline void

497

AT91F_PIO_SetOutput (const AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

498

		     const unsigned int flag)	// \arg  output to be set

499

500

  pPio->PIO_SODR = flag;

501

502

503

//*----------------------------------------------------------------------------

504

//* \fn    AT91F_PIO_ClearOutput

505

//* \brief Set to 0 output PIO

506

//*----------------------------------------------------------------------------

507

static inline void

508

AT91F_PIO_ClearOutput (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

509

		       unsigned int flag)	// \arg  output to be cleared

510

511

  pPio->PIO_CODR = flag;

512

513

514

//*----------------------------------------------------------------------------

515

//* \fn    AT91F_PIO_ForceOutput

516

//* \brief Force output when Direct drive option is enabled

517

//*----------------------------------------------------------------------------

518

static inline void

519

AT91F_PIO_ForceOutput (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

520

		       unsigned int flag)	// \arg  output to be forced

521

522

  pPio->PIO_ODSR = flag;

523

524

525

//*----------------------------------------------------------------------------

526

//* \fn    AT91F_PIO_Enable

527

//* \brief Enable PIO

528

//*----------------------------------------------------------------------------

529

static inline void

530

AT91F_PIO_Enable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

531

		  unsigned int flag)	// \arg  pio to be enabled

532

533

  pPio->PIO_PER = flag;

534

535

536

//*----------------------------------------------------------------------------

537

//* \fn    AT91F_PIO_Disable

538

//* \brief Disable PIO

539

//*----------------------------------------------------------------------------

540

static inline void

541

AT91F_PIO_Disable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

542

		   unsigned int flag)	// \arg  pio to be disabled

543

544

  pPio->PIO_PDR = flag;

545

546

547

//*----------------------------------------------------------------------------

548

//* \fn    AT91F_PIO_GetStatus

549

//* \brief Return PIO Status

550

//*----------------------------------------------------------------------------

551

static inline unsigned int

552

AT91F_PIO_GetStatus (		// \return PIO Status

553

		      AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

554

555

  return pPio->PIO_PSR;

556

557

558

//*----------------------------------------------------------------------------

559

//* \fn    AT91F_PIO_IsSet

560

//* \brief Test if PIO is Set

561

//*----------------------------------------------------------------------------

562

static inline int

563

AT91F_PIO_IsSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

564

		 unsigned int flag)	// \arg  flag to be tested

565

566

  return (AT91F_PIO_GetStatus (pPio) & flag);

567

568

569

//*----------------------------------------------------------------------------

570

//* \fn    AT91F_PIO_OutputEnable

571

//* \brief Output Enable PIO

572

//*----------------------------------------------------------------------------

573

static inline void

574

AT91F_PIO_OutputEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

575

			unsigned int flag)	// \arg  pio output to be enabled

576

577

  pPio->PIO_OER = flag;

578

579

580

//*----------------------------------------------------------------------------

581

//* \fn    AT91F_PIO_OutputDisable

582

//* \brief Output Enable PIO

583

//*----------------------------------------------------------------------------

584

static inline void

585

AT91F_PIO_OutputDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

586

			 unsigned int flag)	// \arg  pio output to be disabled

587

588

  pPio->PIO_ODR = flag;

589

590

591

//*----------------------------------------------------------------------------

592

//* \fn    AT91F_PIO_GetOutputStatus

593

//* \brief Return PIO Output Status

594

//*----------------------------------------------------------------------------

595

static inline unsigned int

596

AT91F_PIO_GetOutputStatus (	// \return PIO Output Status

597

			    AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

598

599

  return pPio->PIO_OSR;

600

601

602

//*----------------------------------------------------------------------------

603

//* \fn    AT91F_PIO_IsOuputSet

604

//* \brief Test if PIO Output is Set

605

//*----------------------------------------------------------------------------

606

static inline int

607

AT91F_PIO_IsOutputSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

608

		       unsigned int flag)	// \arg  flag to be tested

609

610

  return (AT91F_PIO_GetOutputStatus (pPio) & flag);

611

612

613

//*----------------------------------------------------------------------------

614

//* \fn    AT91F_PIO_InputFilterEnable

615

//* \brief Input Filter Enable PIO

616

//*----------------------------------------------------------------------------

617

static inline void

618

AT91F_PIO_InputFilterEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

619

			     unsigned int flag)	// \arg  pio input filter to be enabled

620

621

  pPio->PIO_IFER = flag;

622

623

624

//*----------------------------------------------------------------------------

625

//* \fn    AT91F_PIO_InputFilterDisable

626

//* \brief Input Filter Disable PIO

627

//*----------------------------------------------------------------------------

628

static inline void

629

AT91F_PIO_InputFilterDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

630

			      unsigned int flag)	// \arg  pio input filter to be disabled

631

632

  pPio->PIO_IFDR = flag;

633

634

635

//*----------------------------------------------------------------------------

636

//* \fn    AT91F_PIO_GetInputFilterStatus

637

//* \brief Return PIO Input Filter Status

638

//*----------------------------------------------------------------------------

639

static inline unsigned int

640

AT91F_PIO_GetInputFilterStatus (	// \return PIO Input Filter Status

641

				 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

642

643

  return pPio->PIO_IFSR;

644

645

646

//*----------------------------------------------------------------------------

647

//* \fn    AT91F_PIO_IsInputFilterSet

648

//* \brief Test if PIO Input filter is Set

649

//*----------------------------------------------------------------------------

650

static inline int

651

AT91F_PIO_IsInputFilterSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

652

			    unsigned int flag)	// \arg  flag to be tested

653

654

  return (AT91F_PIO_GetInputFilterStatus (pPio) & flag);

655

656

657

//*----------------------------------------------------------------------------

658

//* \fn    AT91F_PIO_GetOutputDataStatus

659

//* \brief Return PIO Output Data Status

660

//*----------------------------------------------------------------------------

661

static inline unsigned int

662

AT91F_PIO_GetOutputDataStatus (	// \return PIO Output Data Status

663

				AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

664

665

  return pPio->PIO_ODSR;

666

667

668

//*----------------------------------------------------------------------------

669

//* \fn    AT91F_PIO_InterruptEnable

670

//* \brief Enable PIO Interrupt

671

//*----------------------------------------------------------------------------

672

static inline void

673

AT91F_PIO_InterruptEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

674

			   unsigned int flag)	// \arg  pio interrupt to be enabled

675

676

  pPio->PIO_IER = flag;

677

678

679

//*----------------------------------------------------------------------------

680

//* \fn    AT91F_PIO_InterruptDisable

681

//* \brief Disable PIO Interrupt

682

//*----------------------------------------------------------------------------

683

static inline void

684

AT91F_PIO_InterruptDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

685

			    unsigned int flag)	// \arg  pio interrupt to be disabled

686

687

  pPio->PIO_IDR = flag;

688

689

690

//*----------------------------------------------------------------------------

691

//* \fn    AT91F_PIO_GetInterruptMaskStatus

692

//* \brief Return PIO Interrupt Mask Status

693

//*----------------------------------------------------------------------------

694

static inline unsigned int

695

AT91F_PIO_GetInterruptMaskStatus (	// \return PIO Interrupt Mask Status

696

				   AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

697

698

  return pPio->PIO_IMR;

699

700

701

//*----------------------------------------------------------------------------

702

//* \fn    AT91F_PIO_GetInterruptStatus

703

//* \brief Return PIO Interrupt Status

704

//*----------------------------------------------------------------------------

705

static inline unsigned int

706

AT91F_PIO_GetInterruptStatus (	// \return PIO Interrupt Status

707

			       AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

708

709

  return pPio->PIO_ISR;

710

711

712

//*----------------------------------------------------------------------------

713

//* \fn    AT91F_PIO_IsInterruptMasked

714

//* \brief Test if PIO Interrupt is Masked

715

//*----------------------------------------------------------------------------

716

static inline int

717

AT91F_PIO_IsInterruptMasked (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

718

			     unsigned int flag)	// \arg  flag to be tested

719

720

  return (AT91F_PIO_GetInterruptMaskStatus (pPio) & flag);

721

722

723

//*----------------------------------------------------------------------------

724

//* \fn    AT91F_PIO_IsInterruptSet

725

//* \brief Test if PIO Interrupt is Set

726

//*----------------------------------------------------------------------------

727

static inline int

728

AT91F_PIO_IsInterruptSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

729

			  unsigned int flag)	// \arg  flag to be tested

730

731

  return (AT91F_PIO_GetInterruptStatus (pPio) & flag);

732

733

734

//*----------------------------------------------------------------------------

735

//* \fn    AT91F_PIO_MultiDriverEnable

736

//* \brief Multi Driver Enable PIO

737

//*----------------------------------------------------------------------------

738

static inline void

739

AT91F_PIO_MultiDriverEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

740

			     unsigned int flag)	// \arg  pio to be enabled

741

742

  pPio->PIO_MDER = flag;

743

744

745

//*----------------------------------------------------------------------------

746

//* \fn    AT91F_PIO_MultiDriverDisable

747

//* \brief Multi Driver Disable PIO

748

//*----------------------------------------------------------------------------

749

static inline void

750

AT91F_PIO_MultiDriverDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

751

			      unsigned int flag)	// \arg  pio to be disabled

752

753

  pPio->PIO_MDDR = flag;

754

755

756

//*----------------------------------------------------------------------------

757

//* \fn    AT91F_PIO_GetMultiDriverStatus

758

//* \brief Return PIO Multi Driver Status

759

//*----------------------------------------------------------------------------

760

static inline unsigned int

761

AT91F_PIO_GetMultiDriverStatus (	// \return PIO Multi Driver Status

762

				 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

763

764

  return pPio->PIO_MDSR;

765

766

767

//*----------------------------------------------------------------------------

768

//* \fn    AT91F_PIO_IsMultiDriverSet

769

//* \brief Test if PIO MultiDriver is Set

770

//*----------------------------------------------------------------------------

771

static inline int

772

AT91F_PIO_IsMultiDriverSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

773

			    unsigned int flag)	// \arg  flag to be tested

774

775

  return (AT91F_PIO_GetMultiDriverStatus (pPio) & flag);

776

777

778

//*----------------------------------------------------------------------------

779

//* \fn    AT91F_PIO_A_RegisterSelection

780

//* \brief PIO A Register Selection

781

//*----------------------------------------------------------------------------

782

static inline void

783

AT91F_PIO_A_RegisterSelection (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

784

			       unsigned int flag)	// \arg  pio A register selection

785

786

  pPio->PIO_ASR = flag;

787

788

789

//*----------------------------------------------------------------------------

790

//* \fn    AT91F_PIO_B_RegisterSelection

791

//* \brief PIO B Register Selection

792

//*----------------------------------------------------------------------------

793

static inline void

794

AT91F_PIO_B_RegisterSelection (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

795

			       unsigned int flag)	// \arg  pio B register selection

796

797

  pPio->PIO_BSR = flag;

798

799

800

//*----------------------------------------------------------------------------

801

//* \fn    AT91F_PIO_Get_AB_RegisterStatus

802

//* \brief Return PIO Interrupt Status

803

//*----------------------------------------------------------------------------

804

static inline unsigned int

805

AT91F_PIO_Get_AB_RegisterStatus (	// \return PIO AB Register Status

806

				  AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

807

808

  return pPio->PIO_ABSR;

809

810

811

//*----------------------------------------------------------------------------

812

//* \fn    AT91F_PIO_IsAB_RegisterSet

813

//* \brief Test if PIO AB Register is Set

814

//*----------------------------------------------------------------------------

815

static inline int

816

AT91F_PIO_IsAB_RegisterSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

817

			    unsigned int flag)	// \arg  flag to be tested

818

819

  return (AT91F_PIO_Get_AB_RegisterStatus (pPio) & flag);

820

821

822

//*----------------------------------------------------------------------------

823

//* \fn    AT91F_PIO_OutputWriteEnable

824

//* \brief Output Write Enable PIO

825

//*----------------------------------------------------------------------------

826

static inline void

827

AT91F_PIO_OutputWriteEnable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

828

			     unsigned int flag)	// \arg  pio output write to be enabled

829

830

  pPio->PIO_OWER = flag;

831

832

833

//*----------------------------------------------------------------------------

834

//* \fn    AT91F_PIO_OutputWriteDisable

835

//* \brief Output Write Disable PIO

836

//*----------------------------------------------------------------------------

837

static inline void

838

AT91F_PIO_OutputWriteDisable (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

839

			      unsigned int flag)	// \arg  pio output write to be disabled

840

841

  pPio->PIO_OWDR = flag;

842

843

844

//*----------------------------------------------------------------------------

845

//* \fn    AT91F_PIO_GetOutputWriteStatus

846

//* \brief Return PIO Output Write Status

847

//*----------------------------------------------------------------------------

848

static inline unsigned int

849

AT91F_PIO_GetOutputWriteStatus (	// \return PIO Output Write Status

850

				 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

851

852

  return pPio->PIO_OWSR;

853

854

855

//*----------------------------------------------------------------------------

856

//* \fn    AT91F_PIO_IsOutputWriteSet

857

//* \brief Test if PIO OutputWrite is Set

858

//*----------------------------------------------------------------------------

859

static inline int

860

AT91F_PIO_IsOutputWriteSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

861

			    unsigned int flag)	// \arg  flag to be tested

862

863

  return (AT91F_PIO_GetOutputWriteStatus (pPio) & flag);

864

865

866

//*----------------------------------------------------------------------------

867

//* \fn    AT91F_PIO_GetCfgPullup

868

//* \brief Return PIO Configuration Pullup

869

//*----------------------------------------------------------------------------

870

static inline unsigned int

871

AT91F_PIO_GetCfgPullup (	// \return PIO Configuration Pullup

872

			 AT91PS_PIO pPio)	// \arg  pointer to a PIO controller

873

874

  return pPio->PIO_PPUSR;

875

876

877

//*----------------------------------------------------------------------------

878

//* \fn    AT91F_PIO_IsOutputDataStatusSet

879

//* \brief Test if PIO Output Data Status is Set

880

//*----------------------------------------------------------------------------

881

static inline int

882

AT91F_PIO_IsOutputDataStatusSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

883

				 unsigned int flag)	// \arg  flag to be tested

884

885

  return (AT91F_PIO_GetOutputDataStatus (pPio) & flag);

886

887

888

//*----------------------------------------------------------------------------

889

//* \fn    AT91F_PIO_IsCfgPullupStatusSet

890

//* \brief Test if PIO Configuration Pullup Status is Set

891

//*----------------------------------------------------------------------------

892

static inline int

893

AT91F_PIO_IsCfgPullupStatusSet (AT91PS_PIO pPio,	// \arg  pointer to a PIO controller

894

				unsigned int flag)	// \arg  flag to be tested

895

896

  return (~AT91F_PIO_GetCfgPullup (pPio) & flag);

897

898

899

/* *****************************************************************************

900

                SOFTWARE API FOR PMC

901

   ***************************************************************************** */

902

//*----------------------------------------------------------------------------

903

//* \fn    AT91F_PMC_CfgSysClkEnableReg

904

//* \brief Configure the System Clock Enable Register of the PMC controller

905

//*----------------------------------------------------------------------------

906

static inline void

907

AT91F_PMC_CfgSysClkEnableReg (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

908

			      unsigned int mode)

909

910

  //* Write to the SCER register

911

  pPMC->PMC_SCER = mode;

912

913

914

//*----------------------------------------------------------------------------

915

//* \fn    AT91F_PMC_CfgSysClkDisableReg

916

//* \brief Configure the System Clock Disable Register of the PMC controller

917

//*----------------------------------------------------------------------------

918

static inline void

919

AT91F_PMC_CfgSysClkDisableReg (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

920

			       unsigned int mode)

921

922

  //* Write to the SCDR register

923

  pPMC->PMC_SCDR = mode;

924

925

926

//*----------------------------------------------------------------------------

927

//* \fn    AT91F_PMC_GetSysClkStatusReg

928

//* \brief Return the System Clock Status Register of the PMC controller

929

//*----------------------------------------------------------------------------

930

static inline unsigned int

931

AT91F_PMC_GetSysClkStatusReg (AT91PS_PMC pPMC	// pointer to a CAN controller

932

933

934

  return pPMC->PMC_SCSR;

935

936

937

//*----------------------------------------------------------------------------

938

//* \fn    AT91F_PMC_EnablePeriphClock

939

//* \brief Enable peripheral clock

940

//*----------------------------------------------------------------------------

941

static inline void

942

AT91F_PMC_EnablePeriphClock (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

943

			     unsigned int periphIds)	// \arg IDs of peripherals to enable

944

945

  pPMC->PMC_PCER = periphIds;

946

947

948

//*----------------------------------------------------------------------------

949

//* \fn    AT91F_PMC_DisablePeriphClock

950

//* \brief Disable peripheral clock

951

//*----------------------------------------------------------------------------

952

static inline void

953

AT91F_PMC_DisablePeriphClock (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

954

			      unsigned int periphIds)	// \arg IDs of peripherals to enable

955

956

  pPMC->PMC_PCDR = periphIds;

957

958

959

//*----------------------------------------------------------------------------

960

//* \fn    AT91F_PMC_GetPeriphClock

961

//* \brief Get peripheral clock status

962

//*----------------------------------------------------------------------------

963

static inline unsigned int

964

AT91F_PMC_GetPeriphClock (AT91PS_PMC pPMC)	// \arg pointer to PMC controller

965

966

  return pPMC->PMC_PCSR;

967

968

969

//*----------------------------------------------------------------------------

970

//* \fn    AT91F_CKGR_CfgMainOscillatorReg

971

//* \brief Cfg the main oscillator

972

//*----------------------------------------------------------------------------

973

static inline void

974

AT91F_CKGR_CfgMainOscillatorReg (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller

975

				 unsigned int mode)

976

977

  pCKGR->CKGR_MOR = mode;

978

979

980

//*----------------------------------------------------------------------------

981

//* \fn    AT91F_CKGR_GetMainOscillatorReg

982

//* \brief Cfg the main oscillator

983

//*----------------------------------------------------------------------------

984

static inline unsigned int

985

AT91F_CKGR_GetMainOscillatorReg (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller

986

987

  return pCKGR->CKGR_MOR;

988

989

990

//*----------------------------------------------------------------------------

991

//* \fn    AT91F_CKGR_EnableMainOscillator

992

//* \brief Enable the main oscillator

993

//*----------------------------------------------------------------------------

994

static inline void

995

AT91F_CKGR_EnableMainOscillator (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller

996

997

  pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;

998

999

1000

//*----------------------------------------------------------------------------

1001

//* \fn    AT91F_CKGR_DisableMainOscillator

1002

//* \brief Disable the main oscillator

1003

//*----------------------------------------------------------------------------

1004

static inline void

1005

AT91F_CKGR_DisableMainOscillator (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller

1006

1007

  pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;

1008

1009

1010

//*----------------------------------------------------------------------------

1011

//* \fn    AT91F_CKGR_CfgMainOscStartUpTime

1012

//* \brief Cfg MOR Register according to the main osc startup time

1013

//*----------------------------------------------------------------------------

1014

static inline void

1015

AT91F_CKGR_CfgMainOscStartUpTime (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller

1016

				  unsigned int startup_time,	// \arg main osc startup time in microsecond (us)

1017

				  unsigned int slowClock)	// \arg slowClock in Hz

1018

1019

  pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;

1020

  pCKGR->CKGR_MOR |= ((slowClock * startup_time) / (8 * 1000000)) << 8;

1021

1022

1023

//*----------------------------------------------------------------------------

1024

//* \fn    AT91F_CKGR_GetMainClockFreqReg

1025

//* \brief Cfg the main oscillator

1026

//*----------------------------------------------------------------------------

1027

static inline unsigned int

1028

AT91F_CKGR_GetMainClockFreqReg (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller

1029

1030

  return pCKGR->CKGR_MCFR;

1031

1032

1033

//*----------------------------------------------------------------------------

1034

//* \fn    AT91F_CKGR_GetMainClock

1035

//* \brief Return Main clock in Hz

1036

//*----------------------------------------------------------------------------

1037

static inline unsigned int

1038

AT91F_CKGR_GetMainClock (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller

1039

			 unsigned int slowClock)	// \arg slowClock in Hz

1040

1041

  return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;

1042

1043

1044

//*----------------------------------------------------------------------------

1045

//* \fn    AT91F_PMC_CfgMCKReg

1046

//* \brief Cfg Master Clock Register

1047

//*----------------------------------------------------------------------------

1048

static inline void

1049

AT91F_PMC_CfgMCKReg (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

1050

		     unsigned int mode)

1051

1052

  pPMC->PMC_MCKR = mode;

1053

1054

1055

//*----------------------------------------------------------------------------

1056

//* \fn    AT91F_PMC_GetMCKReg

1057

//* \brief Return Master Clock Register

1058

//*----------------------------------------------------------------------------

1059

static inline unsigned int

1060

AT91F_PMC_GetMCKReg (AT91PS_PMC pPMC)	// \arg pointer to PMC controller

1061

1062

  return pPMC->PMC_MCKR;

1063

1064

1065

//*------------------------------------------------------------------------------

1066

//* \fn    AT91F_PMC_GetMasterClock

1067

//* \brief Return master clock in Hz which correponds to processor clock for ARM7

1068

//*------------------------------------------------------------------------------

1069

extern unsigned int AT91F_PMC_GetMasterClock (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

1070

					      AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller

1071

					      unsigned int slowClock);	// \arg slowClock in Hz

1072

1073

//*----------------------------------------------------------------------------

1074

//* \fn    AT91F_PMC_EnablePCK

1075

//* \brief Enable peripheral clock

1076

//*----------------------------------------------------------------------------

1077

static inline void

1078

AT91F_PMC_EnablePCK (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

1079

		     unsigned int pck,	// \arg Peripheral clock identifier 0 .. 7

1080

		     unsigned int mode)

1081

1082

  pPMC->PMC_PCKR[pck] = mode;

1083

  pPMC->PMC_SCER = (1 << pck) << 8;

1084

1085

1086

//*----------------------------------------------------------------------------

1087

//* \fn    AT91F_PMC_DisablePCK

1088

//* \brief Enable peripheral clock

1089

//*----------------------------------------------------------------------------

1090

static inline void

1091

AT91F_PMC_DisablePCK (AT91PS_PMC pPMC,	// \arg pointer to PMC controller

1092

		      unsigned int pck)	// \arg Peripheral clock identifier 0 .. 7

1093

1094

  pPMC->PMC_SCDR = (1 << pck) << 8;

1095

1096

1097

//*----------------------------------------------------------------------------

1098

//* \fn    AT91F_PMC_EnableIt

1099

//* \brief Enable PMC interrupt

1100

//*----------------------------------------------------------------------------

1101

static inline void

1102

AT91F_PMC_EnableIt (AT91PS_PMC pPMC,	// pointer to a PMC controller

1103

		    unsigned int flag)	// IT to be enabled

1104

1105

  //* Write to the IER register

1106

  pPMC->PMC_IER = flag;

1107

1108

1109

//*----------------------------------------------------------------------------

1110

//* \fn    AT91F_PMC_DisableIt

1111

//* \brief Disable PMC interrupt

1112

//*----------------------------------------------------------------------------

1113

static inline void

1114

AT91F_PMC_DisableIt (AT91PS_PMC pPMC,	// pointer to a PMC controller

1115

		     unsigned int flag)	// IT to be disabled

1116

1117

  //* Write to the IDR register

1118

  pPMC->PMC_IDR = flag;

1119

1120

1121

//*----------------------------------------------------------------------------

1122

//* \fn    AT91F_PMC_GetStatus

1123

//* \brief Return PMC Interrupt Status

1124

//*----------------------------------------------------------------------------

1125

static inline unsigned int

1126

AT91F_PMC_GetStatus (		// \return PMC Interrupt Status

1127

		      AT91PS_PMC pPMC)	// pointer to a PMC controller

1128

1129

  return pPMC->PMC_SR;

1130

1131

1132

//*----------------------------------------------------------------------------

1133

//* \fn    AT91F_PMC_GetInterruptMaskStatus

1134

//* \brief Return PMC Interrupt Mask Status

1135

//*----------------------------------------------------------------------------

1136

static inline unsigned int

1137

AT91F_PMC_GetInterruptMaskStatus (	// \return PMC Interrupt Mask Status

1138

				   AT91PS_PMC pPMC)	// pointer to a PMC controller

1139

1140

  return pPMC->PMC_IMR;

1141

1142

1143

//*----------------------------------------------------------------------------

1144

//* \fn    AT91F_PMC_IsInterruptMasked

1145

//* \brief Test if PMC Interrupt is Masked

1146

//*----------------------------------------------------------------------------

1147

static inline unsigned int

1148

AT91F_PMC_IsInterruptMasked (AT91PS_PMC pPMC,	// \arg  pointer to a PMC controller

1149

			     unsigned int flag)	// \arg  flag to be tested

1150

1151

  return (AT91F_PMC_GetInterruptMaskStatus (pPMC) & flag);

1152

1153

1154

//*----------------------------------------------------------------------------

1155

//* \fn    AT91F_PMC_IsStatusSet

1156

//* \brief Test if PMC Status is Set

1157

//*----------------------------------------------------------------------------

1158

static inline unsigned int

1159

AT91F_PMC_IsStatusSet (AT91PS_PMC pPMC,	// \arg  pointer to a PMC controller

1160

		       unsigned int flag)	// \arg  flag to be tested

1161

1162

  return (AT91F_PMC_GetStatus (pPMC) & flag);

1163

1164

1165

// ----------------------------------------------------------------------------

1166

//  \fn    AT91F_CKGR_CfgPLLReg

1167

//  \brief Cfg the PLL Register

1168

// ----------------------------------------------------------------------------

1169

static inline void

1170

AT91F_CKGR_CfgPLLReg (AT91PS_CKGR pCKGR,	// \arg pointer to CKGR controller

1171

		      unsigned int mode)

1172

1173

  pCKGR->CKGR_PLLR = mode;

1174

1175

1176

// ----------------------------------------------------------------------------

1177

//  \fn    AT91F_CKGR_GetPLLReg

1178

//  \brief Get the PLL Register

1179

// ----------------------------------------------------------------------------

1180

static inline unsigned int

1181

AT91F_CKGR_GetPLLReg (AT91PS_CKGR pCKGR)	// \arg pointer to CKGR controller

1182

1183

  return pCKGR->CKGR_PLLR;

/* *****************************************************************************

1189

                SOFTWARE API FOR RSTC

1190

   ***************************************************************************** */

1191

//*----------------------------------------------------------------------------

1192

//* \fn    AT91F_RSTSoftReset

1193

//* \brief Start Software Reset

1194

//*----------------------------------------------------------------------------

1195

static inline void

1196

AT91F_RSTSoftReset (AT91PS_RSTC pRSTC, unsigned int reset)

1197

1198

  pRSTC->RSTC_RCR = (0xA5000000 | reset);

1199

1200

1201

//*----------------------------------------------------------------------------

1202

//* \fn    AT91F_RSTSetMode

1203

//* \brief Set Reset Mode

1204

//*----------------------------------------------------------------------------

1205

static inline void

1206

AT91F_RSTSetMode (AT91PS_RSTC pRSTC, unsigned int mode)

1207

1208

  pRSTC->RSTC_RMR = (0xA5000000 | mode);

1209

1210

1211

//*----------------------------------------------------------------------------

1212

//* \fn    AT91F_RSTGetMode

1213

//* \brief Get Reset Mode

1214

//*----------------------------------------------------------------------------

1215

static inline unsigned int

1216

AT91F_RSTGetMode (AT91PS_RSTC pRSTC)

1217

1218

  return (pRSTC->RSTC_RMR);

1219

1220

1221

//*----------------------------------------------------------------------------

1222

//* \fn    AT91F_RSTGetStatus

1223

//* \brief Get Reset Status

1224

//*----------------------------------------------------------------------------

1225

static inline unsigned int

1226

AT91F_RSTGetStatus (AT91PS_RSTC pRSTC)

1227

1228

  return (pRSTC->RSTC_RSR);

1229

1230

1231

//*----------------------------------------------------------------------------

1232

//* \fn    AT91F_RSTIsSoftRstActive

1233

//* \brief Return !=0 if software reset is still not completed

1234

//*----------------------------------------------------------------------------

1235

static inline unsigned int

1236

AT91F_RSTIsSoftRstActive (AT91PS_RSTC pRSTC)

1237

1238

  return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);

1239

1240

1241

/* *****************************************************************************

1242

                SOFTWARE API FOR RTTC

1243

   ***************************************************************************** */

1244

//*--------------------------------------------------------------------------------------

1245

//* \fn     AT91F_SetRTT_TimeBase()

1246

//* \brief  Set the RTT prescaler according to the TimeBase in ms

1247

//*--------------------------------------------------------------------------------------

1248

static inline unsigned int

1249

AT91F_RTTSetTimeBase (AT91PS_RTTC pRTTC, unsigned int ms)

1250

1251

  if (ms > 2000)

1252

    return 1;			// AT91C_TIME_OUT_OF_RANGE

1253

  pRTTC->RTTC_RTMR &= ~0xFFFF;

1254

  pRTTC->RTTC_RTMR |= (((ms << 15) / 1000) & 0xFFFF);

1255

  return 0;

1256

1257

1258

//*--------------------------------------------------------------------------------------

1259

//* \fn     AT91F_RTTSetPrescaler()

1260

//* \brief  Set the new prescaler value

1261

//*--------------------------------------------------------------------------------------

1262

static inline unsigned int

1263

AT91F_RTTSetPrescaler (AT91PS_RTTC pRTTC, unsigned int rtpres)

1264

1265

  pRTTC->RTTC_RTMR &= ~0xFFFF;

1266

  pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);

1267

  return (pRTTC->RTTC_RTMR);

1268

1269

1270

//*--------------------------------------------------------------------------------------

1271

//* \fn     AT91F_RTTRestart()

1272

//* \brief  Restart the RTT prescaler

1273

//*--------------------------------------------------------------------------------------

1274

static inline void

1275

AT91F_RTTRestart (AT91PS_RTTC pRTTC)

1276

1277

  pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;

//*--------------------------------------------------------------------------------------

1282

//* \fn     AT91F_RTT_SetAlarmINT()

1283

//* \brief  Enable RTT Alarm Interrupt

1284

//*--------------------------------------------------------------------------------------

1285

static inline void

1286

AT91F_RTTSetAlarmINT (AT91PS_RTTC pRTTC)

1287

1288

  pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;

1289

1290

1291

//*--------------------------------------------------------------------------------------

1292

//* \fn     AT91F_RTT_ClearAlarmINT()

1293

//* \brief  Disable RTT Alarm Interrupt

1294

//*--------------------------------------------------------------------------------------

1295

static inline void

1296

AT91F_RTTClearAlarmINT (AT91PS_RTTC pRTTC)

1297

1298

  pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;

1299

1300

1301

//*--------------------------------------------------------------------------------------

1302

//* \fn     AT91F_RTT_SetRttIncINT()

1303

//* \brief  Enable RTT INC Interrupt

1304

//*--------------------------------------------------------------------------------------

1305

static inline void

1306

AT91F_RTTSetRttIncINT (AT91PS_RTTC pRTTC)

1307

1308

  pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;

1309

1310

1311

//*--------------------------------------------------------------------------------------

1312

//* \fn     AT91F_RTT_ClearRttIncINT()

1313

//* \brief  Disable RTT INC Interrupt

1314

//*--------------------------------------------------------------------------------------

1315

static inline void

1316

AT91F_RTTClearRttIncINT (AT91PS_RTTC pRTTC)

1317

1318

  pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;

1319

1320

1321

//*--------------------------------------------------------------------------------------

1322

//* \fn     AT91F_RTT_SetAlarmValue()

1323

//* \brief  Set RTT Alarm Value

1324

//*--------------------------------------------------------------------------------------

1325

static inline void

1326

AT91F_RTTSetAlarmValue (AT91PS_RTTC pRTTC, unsigned int _alarm)

1327

1328

  pRTTC->RTTC_RTAR = _alarm;

1329

1330

1331

//*--------------------------------------------------------------------------------------

1332

//* \fn     AT91F_RTT_GetAlarmValue()

1333

//* \brief  Get RTT Alarm Value

1334

//*--------------------------------------------------------------------------------------

1335

static inline unsigned int

1336

AT91F_RTTGetAlarmValue (AT91PS_RTTC pRTTC)

1337

1338

  return (pRTTC->RTTC_RTAR);

1339

1340

1341

//*--------------------------------------------------------------------------------------

1342

//* \fn     AT91F_RTTGetStatus()

1343

//* \brief  Read the RTT status

1344

//*--------------------------------------------------------------------------------------

1345

static inline unsigned int

1346

AT91F_RTTGetStatus (AT91PS_RTTC pRTTC)

1347

1348

  return (pRTTC->RTTC_RTSR);

1349

1350

1351

//*--------------------------------------------------------------------------------------

1352

//* \fn     AT91F_RTT_ReadValue()

1353

//* \brief  Read the RTT value

1354

//*--------------------------------------------------------------------------------------

1355

extern unsigned int AT91F_RTTReadValue (AT91PS_RTTC pRTTC);

1356

1357

/* *****************************************************************************

1358

                SOFTWARE API FOR PITC

1359

   ***************************************************************************** */

1360

//*----------------------------------------------------------------------------

1361

//* \fn    AT91F_PITInit

1362

//* \brief System timer init : period in ?second, system clock freq in MHz

1363

//*----------------------------------------------------------------------------

1364

static inline void

1365

AT91F_PITInit (AT91PS_PITC pPITC,

1366

	       unsigned int period, unsigned int pit_frequency)

1367

1368

  pPITC->PITC_PIMR = period ? (period * pit_frequency + 8) >> 4 : 0;	// +8 to avoid %10 and /10

1369

  pPITC->PITC_PIMR |= AT91C_PITC_PITEN;

1370

1371

1372

//*----------------------------------------------------------------------------

1373

//* \fn    AT91F_PITSetPIV

1374

//* \brief Set the PIT Periodic Interval Value

1375

//*----------------------------------------------------------------------------

1376

static inline void

1377

AT91F_PITSetPIV (AT91PS_PITC pPITC, unsigned int piv)

1378

1379

  pPITC->PITC_PIMR =

1380

    piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));

1381

1382

1383

//*----------------------------------------------------------------------------

1384

//* \fn    AT91F_PITEnableInt

1385

//* \brief Enable PIT periodic interrupt

1386

//*----------------------------------------------------------------------------

1387

static inline void

1388

AT91F_PITEnableInt (AT91PS_PITC pPITC)

1389

1390

  pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;

1391

1392

1393

//*----------------------------------------------------------------------------

1394

//* \fn    AT91F_PITDisableInt

1395

//* \brief Disable PIT periodic interrupt

1396

//*----------------------------------------------------------------------------

1397

static inline void

1398

AT91F_PITDisableInt (AT91PS_PITC pPITC)

1399

1400

  pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;

1401

1402

1403

//*----------------------------------------------------------------------------

1404

//* \fn    AT91F_PITGetMode

1405

//* \brief Read PIT mode register

1406

//*----------------------------------------------------------------------------

1407

static inline unsigned int

1408

AT91F_PITGetMode (AT91PS_PITC pPITC)

1409

1410

  return (pPITC->PITC_PIMR);

1411

1412

1413

//*----------------------------------------------------------------------------

1414

//* \fn    AT91F_PITGetStatus

1415

//* \brief Read PIT status register

1416

//*----------------------------------------------------------------------------

1417

static inline unsigned int

1418

AT91F_PITGetStatus (AT91PS_PITC pPITC)

1419

1420

  return (pPITC->PITC_PISR);

1421

1422

1423

//*----------------------------------------------------------------------------

1424

//* \fn    AT91F_PITGetPIIR

1425

//* \brief Read PIT CPIV and PICNT without ressetting the counters

1426

//*----------------------------------------------------------------------------

1427

static inline unsigned int

1428

AT91F_PITGetPIIR (AT91PS_PITC pPITC)

1429

1430

  return (pPITC->PITC_PIIR);

1431

1432

1433

//*----------------------------------------------------------------------------

1434

//* \fn    AT91F_PITGetPIVR

1435

//* \brief Read System timer CPIV and PICNT without ressetting the counters

1436

//*----------------------------------------------------------------------------

1437

static inline unsigned int

1438

AT91F_PITGetPIVR (AT91PS_PITC pPITC)

1439

1440

  return (pPITC->PITC_PIVR);

1441

1442

1443

/* *****************************************************************************

1444

                SOFTWARE API FOR WDTC

1445

   ***************************************************************************** */

1446

//*----------------------------------------------------------------------------

1447

//* \fn    AT91F_WDTSetMode

1448

//* \brief Set Watchdog Mode Register

1449

//*----------------------------------------------------------------------------

1450

static inline void

1451

AT91F_WDTSetMode (AT91PS_WDTC pWDTC, unsigned int Mode)

1452

1453

  pWDTC->WDTC_WDMR = Mode;

1454

1455

1456

//*----------------------------------------------------------------------------

1457

//* \fn    AT91F_WDTRestart

1458

//* \brief Restart Watchdog

1459

//*----------------------------------------------------------------------------

1460

static inline void

1461

AT91F_WDTRestart (AT91PS_WDTC pWDTC)

1462

1463

  pWDTC->WDTC_WDCR = 0xA5000001;

1464

1465

1466

//*----------------------------------------------------------------------------

1467

//* \fn    AT91F_WDTSGettatus

1468

//* \brief Get Watchdog Status

1469

//*----------------------------------------------------------------------------

1470

static inline unsigned int

1471

AT91F_WDTSGettatus (AT91PS_WDTC pWDTC)

1472

1473

  return (pWDTC->WDTC_WDSR & 0x3);

1474

1475

1476

//*----------------------------------------------------------------------------

1477

//* \fn    AT91F_WDTGetPeriod

1478

//* \brief Translate ms into Watchdog Compatible value

1479

//*----------------------------------------------------------------------------

1480

static inline unsigned int

1481

AT91F_WDTGetPeriod (unsigned int ms)

1482

1483

  if ((ms < 4) || (ms > 16000))

1484

    return 0;

1485

  return ((ms << 8) / 1000);

1486

1487

1488

/* *****************************************************************************

1489

                SOFTWARE API FOR VREG

1490

   ***************************************************************************** */

1491

//*----------------------------------------------------------------------------

1492

//* \fn    AT91F_VREG_Enable_LowPowerMode

1493

//* \brief Enable VREG Low Power Mode

1494

//*----------------------------------------------------------------------------

1495

static inline void

1496

AT91F_VREG_Enable_LowPowerMode (AT91PS_VREG pVREG)

1497

1498

  pVREG->VREG_MR |= AT91C_VREG_PSTDBY;

1499

1500

1501

//*----------------------------------------------------------------------------

1502

//* \fn    AT91F_VREG_Disable_LowPowerMode

1503

//* \brief Disable VREG Low Power Mode

1504

//*----------------------------------------------------------------------------

1505

static inline void

1506

AT91F_VREG_Disable_LowPowerMode (AT91PS_VREG pVREG)

1507

1508

  pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;

1509

}				/* *****************************************************************************

1510

				   SOFTWARE API FOR MC

1511

				   ***************************************************************************** */

1512

1513

#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24)	// (MC) Correct Protect Key

1514

1515

//*----------------------------------------------------------------------------

1516

//* \fn    AT91F_MC_Remap

1517

//* \brief Make Remap

1518

//*----------------------------------------------------------------------------

1519

static inline void

1520

AT91F_MC_Remap (void)		//

1521

1522

  AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;

1523

1524

  pMC->MC_RCR = AT91C_MC_RCB;

1525

1526

1527

//*----------------------------------------------------------------------------

1528

//* \fn    AT91F_MC_EFC_CfgModeReg

1529

//* \brief Configure the EFC Mode Register of the MC controller

1530

//*----------------------------------------------------------------------------

1531

static inline void

1532

AT91F_MC_EFC_CfgModeReg (AT91PS_MC pMC,	// pointer to a MC controller

1533

			 unsigned int mode)	// mode register

1534

1535

  // Write to the FMR register

1536

  pMC->MC_FMR = mode;

1537

1538

1539

//*----------------------------------------------------------------------------

1540

//* \fn    AT91F_MC_EFC_GetModeReg

1541

//* \brief Return MC EFC Mode Regsiter

1542

//*----------------------------------------------------------------------------

1543

static inline unsigned int

1544

AT91F_MC_EFC_GetModeReg (AT91PS_MC pMC)	// pointer to a MC controller

1545

1546

  return pMC->MC_FMR;

1547

1548

1549

//*----------------------------------------------------------------------------

1550

//* \fn    AT91F_MC_EFC_ComputeFMCN

1551

//* \brief Return MC EFC Mode Regsiter

1552

//*----------------------------------------------------------------------------

1553

static inline unsigned int

1554

AT91F_MC_EFC_ComputeFMCN (int master_clock)	// master clock in Hz

1555

1556

  return (master_clock / 1000000 + 2);

1557

1558

1559

//*----------------------------------------------------------------------------

1560

//* \fn    AT91F_MC_EFC_PerformCmd

1561

//* \brief Perform EFC Command

1562

//*----------------------------------------------------------------------------

1563

static inline void

1564

AT91F_MC_EFC_PerformCmd (AT91PS_MC pMC,	// pointer to a MC controller

1565

			 unsigned int transfer_cmd)

1566

1567

  pMC->MC_FCR = transfer_cmd;

1568

1569

1570

//*----------------------------------------------------------------------------

1571

//* \fn    AT91F_MC_EFC_GetStatus

1572

//* \brief Return MC EFC Status

1573

//*----------------------------------------------------------------------------

1574

static inline unsigned int

1575

AT91F_MC_EFC_GetStatus (AT91PS_MC pMC)	// pointer to a MC controller

1576

1577

  return pMC->MC_FSR;

1578

1579

1580

//*----------------------------------------------------------------------------

1581

//* \fn    AT91F_MC_EFC_IsInterruptMasked

1582

//* \brief Test if EFC MC Interrupt is Masked

1583

//*----------------------------------------------------------------------------

1584

static inline unsigned int

1585

AT91F_MC_EFC_IsInterruptMasked (AT91PS_MC pMC,	// \arg  pointer to a MC controller

1586

				unsigned int flag)	// \arg  flag to be tested

1587

1588

  return (AT91F_MC_EFC_GetModeReg (pMC) & flag);

1589

1590

1591

//*----------------------------------------------------------------------------

1592

//* \fn    AT91F_MC_EFC_IsInterruptSet

1593

//* \brief Test if EFC MC Interrupt is Set

1594

//*----------------------------------------------------------------------------

1595

static inline unsigned int

1596

AT91F_MC_EFC_IsInterruptSet (AT91PS_MC pMC,	// \arg  pointer to a MC controller

1597

			     unsigned int flag)	// \arg  flag to be tested

1598

1599

  return (AT91F_MC_EFC_GetStatus (pMC) & flag);

1600

1601

1602

/* *****************************************************************************

1603

                SOFTWARE API FOR SPI

1604

   ***************************************************************************** */

1605

//*----------------------------------------------------------------------------

1606

//* \fn    AT91F_SPI_CfgCs

1607

//* \brief Configure SPI chip select register

1608

//*----------------------------------------------------------------------------

1609

static inline void

1610

AT91F_SPI_CfgCs (AT91PS_SPI pSPI,	// pointer to a SPI controller

1611

		 int cs,	// SPI cs number (0 to 3)

1612

		 int val)	//  chip select register

1613

1614

  //* Write to the CSR register

1615

  *(pSPI->SPI_CSR + cs) = val;

1616

1617

1618

//*----------------------------------------------------------------------------

1619

//* \fn    AT91F_SPI_EnableIt

1620

//* \brief Enable SPI interrupt

1621

//*----------------------------------------------------------------------------

1622

static inline void

1623

AT91F_SPI_EnableIt (AT91PS_SPI pSPI,	// pointer to a SPI controller

1624

		    unsigned int flag)	// IT to be enabled

1625

1626

  //* Write to the IER register

1627

  pSPI->SPI_IER = flag;

1628

1629

1630

//*----------------------------------------------------------------------------

1631

//* \fn    AT91F_SPI_DisableIt

1632

//* \brief Disable SPI interrupt

1633

//*----------------------------------------------------------------------------

1634

static inline void

1635

AT91F_SPI_DisableIt (AT91PS_SPI pSPI,	// pointer to a SPI controller

1636

		     unsigned int flag)	// IT to be disabled

1637

1638

  //* Write to the IDR register

1639

  pSPI->SPI_IDR = flag;

1640

1641

1642

//*----------------------------------------------------------------------------

1643

//* \fn    AT91F_SPI_Reset

1644

//* \brief Reset the SPI controller

1645

//*----------------------------------------------------------------------------

1646

static inline void

1647

AT91F_SPI_Reset (AT91PS_SPI pSPI	// pointer to a SPI controller

1648

1649

1650

  //* Write to the CR register

1651

  pSPI->SPI_CR = AT91C_SPI_SWRST;

1652

1653

1654

//*----------------------------------------------------------------------------

1655

//* \fn    AT91F_SPI_Enable

1656

//* \brief Enable the SPI controller

1657

//*----------------------------------------------------------------------------

1658

static inline void

1659

AT91F_SPI_Enable (AT91PS_SPI pSPI	// pointer to a SPI controller

1660

1661

1662

  //* Write to the CR register

1663

  pSPI->SPI_CR = AT91C_SPI_SPIEN;

1664

1665

1666

//*----------------------------------------------------------------------------

1667

//* \fn    AT91F_SPI_Disable

1668

//* \brief Disable the SPI controller

1669

//*----------------------------------------------------------------------------

1670

static inline void

1671

AT91F_SPI_Disable (AT91PS_SPI pSPI	// pointer to a SPI controller

1672

1673

1674

  //* Write to the CR register

1675

  pSPI->SPI_CR = AT91C_SPI_SPIDIS;

1676

1677

1678

//*----------------------------------------------------------------------------

1679

//* \fn    AT91F_SPI_CfgMode

1680

//* \brief Enable the SPI controller

1681

//*----------------------------------------------------------------------------

1682

static inline void

1683

AT91F_SPI_CfgMode (AT91PS_SPI pSPI,	// pointer to a SPI controller

1684

		   int mode)	// mode register

1685

1686

  //* Write to the MR register

1687

  pSPI->SPI_MR = mode;

1688

1689

1690

//*----------------------------------------------------------------------------

1691

//* \fn    AT91F_SPI_CfgPCS

1692

//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected

1693

//*----------------------------------------------------------------------------

1694

static inline void

1695

AT91F_SPI_CfgPCS (AT91PS_SPI pSPI,	// pointer to a SPI controller

1696

		  char PCS_Device)	// PCS of the Device

1697

1698

  //* Write to the MR register

1699

  pSPI->SPI_MR &= 0xFFF0FFFF;

1700

  pSPI->SPI_MR |= ((PCS_Device << 16) & AT91C_SPI_PCS);

1701

1702

1703

//*----------------------------------------------------------------------------

1704

//* \fn    AT91F_SPI_ReceiveFrame

1705

//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy

1706

//*----------------------------------------------------------------------------

1707

static inline unsigned int

1708

AT91F_SPI_ReceiveFrame (AT91PS_SPI pSPI,

1709

			unsigned char *pBuffer,

1710

			unsigned int szBuffer,

1711

			unsigned char *pNextBuffer, unsigned int szNextBuffer)

1712

1713

  return AT91F_PDC_ReceiveFrame ((AT91PS_PDC) & (pSPI->SPI_RPR),

1714

				 pBuffer,

1715

				 szBuffer, pNextBuffer, szNextBuffer);

1716

1717

1718

//*----------------------------------------------------------------------------

1719

//* \fn    AT91F_SPI_SendFrame

1720

//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy

1721

//*----------------------------------------------------------------------------

1722

static inline unsigned int

1723

AT91F_SPI_SendFrame (AT91PS_SPI pSPI,

1724

		     const unsigned char *pBuffer,

1725

		     unsigned int szBuffer,

1726

		     const unsigned char *pNextBuffer,

1727

		     unsigned int szNextBuffer)

1728

1729

  return AT91F_PDC_SendFrame ((AT91PS_PDC) & (pSPI->SPI_RPR),

1730

			      pBuffer, szBuffer, pNextBuffer, szNextBuffer);

1731

1732

1733

//*----------------------------------------------------------------------------

1734

//* \fn    AT91F_SPI_Close

1735

//* \brief Close SPI: disable IT disable transfert, close PDC

1736

//*----------------------------------------------------------------------------

1737

extern void AT91F_SPI_Close (AT91PS_SPI pSPI);	// \arg pointer to a SPI controller

1738

1739

//*----------------------------------------------------------------------------

1740

//* \fn    AT91F_SPI_PutChar

1741

//* \brief Send a character,does not check if ready to send

1742

//*----------------------------------------------------------------------------

1743

static inline void

1744

AT91F_SPI_PutChar (AT91PS_SPI pSPI,

1745

		   unsigned int character, unsigned int cs_number)

1746

1747

  unsigned int value_for_cs;

1748

  value_for_cs = (~(1 << cs_number)) & 0xF;	//Place a zero among a 4 ONEs number

1749

  pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);

1750

1751

1752

//*----------------------------------------------------------------------------

1753

//* \fn    AT91F_SPI_GetChar

1754

//* \brief Receive a character,does not check if a character is available

1755

//*----------------------------------------------------------------------------

1756

static inline int

1757

AT91F_SPI_GetChar (const AT91PS_SPI pSPI)

1758

1759

  return ((pSPI->SPI_RDR) & 0xFFFF);

1760

1761

1762

//*----------------------------------------------------------------------------

1763

//* \fn    AT91F_SPI_GetInterruptMaskStatus

1764

//* \brief Return SPI Interrupt Mask Status

1765

//*----------------------------------------------------------------------------

1766

static inline unsigned int

1767

AT91F_SPI_GetInterruptMaskStatus (	// \return SPI Interrupt Mask Status

1768

				   AT91PS_SPI pSpi)	// \arg  pointer to a SPI controller

1769

1770

  return pSpi->SPI_IMR;

1771

1772

1773

//*----------------------------------------------------------------------------

1774

//* \fn    AT91F_SPI_IsInterruptMasked

1775

//* \brief Test if SPI Interrupt is Masked

1776

//*----------------------------------------------------------------------------

1777

static inline int

1778

AT91F_SPI_IsInterruptMasked (AT91PS_SPI pSpi,	// \arg  pointer to a SPI controller

1779

			     unsigned int flag)	// \arg  flag to be tested

1780

1781

  return (AT91F_SPI_GetInterruptMaskStatus (pSpi) & flag);

1782

1783

1784

/* *****************************************************************************

1785

                SOFTWARE API FOR ADC

1786

   ***************************************************************************** */

1787

//*----------------------------------------------------------------------------

1788

//* \fn    AT91F_ADC_EnableIt

1789

//* \brief Enable ADC interrupt

1790

//*----------------------------------------------------------------------------

1791

static inline void

1792

AT91F_ADC_EnableIt (AT91PS_ADC pADC,	// pointer to a ADC controller

1793

		    unsigned int flag)	// IT to be enabled

1794

1795

  //* Write to the IER register

1796

  pADC->ADC_IER = flag;

1797

1798

1799

//*----------------------------------------------------------------------------

1800

//* \fn    AT91F_ADC_DisableIt

1801

//* \brief Disable ADC interrupt

1802

//*----------------------------------------------------------------------------

1803

static inline void

1804

AT91F_ADC_DisableIt (AT91PS_ADC pADC,	// pointer to a ADC controller

1805

		     unsigned int flag)	// IT to be disabled

1806

1807

  //* Write to the IDR register

1808

  pADC->ADC_IDR = flag;

1809

1810

1811

//*----------------------------------------------------------------------------

1812

//* \fn    AT91F_ADC_GetStatus

1813

//* \brief Return ADC Interrupt Status

1814

//*----------------------------------------------------------------------------

1815

static inline unsigned int

1816

AT91F_ADC_GetStatus (		// \return ADC Interrupt Status

1817

		      AT91PS_ADC pADC)	// pointer to a ADC controller

1818

1819

  return pADC->ADC_SR;

1820

1821

1822

//*----------------------------------------------------------------------------

1823

//* \fn    AT91F_ADC_GetInterruptMaskStatus

1824

//* \brief Return ADC Interrupt Mask Status

1825

//*----------------------------------------------------------------------------

1826

static inline unsigned int

1827

AT91F_ADC_GetInterruptMaskStatus (	// \return ADC Interrupt Mask Status

1828

				   AT91PS_ADC pADC)	// pointer to a ADC controller

1829

1830

  return pADC->ADC_IMR;

1831

1832

1833

//*----------------------------------------------------------------------------

1834

//* \fn    AT91F_ADC_IsInterruptMasked

1835

//* \brief Test if ADC Interrupt is Masked

1836

//*----------------------------------------------------------------------------

1837

static inline unsigned int

1838

AT91F_ADC_IsInterruptMasked (AT91PS_ADC pADC,	// \arg  pointer to a ADC controller

1839

			     unsigned int flag)	// \arg  flag to be tested

1840

1841

  return (AT91F_ADC_GetInterruptMaskStatus (pADC) & flag);

1842

1843

1844

//*----------------------------------------------------------------------------

1845

//* \fn    AT91F_ADC_IsStatusSet

1846

//* \brief Test if ADC Status is Set

1847

//*----------------------------------------------------------------------------

1848

static inline unsigned int

1849

AT91F_ADC_IsStatusSet (AT91PS_ADC pADC,	// \arg  pointer to a ADC controller

1850

		       unsigned int flag)	// \arg  flag to be tested

1851

1852

  return (AT91F_ADC_GetStatus (pADC) & flag);

1853

1854

1855

//*----------------------------------------------------------------------------

1856

//* \fn    AT91F_ADC_CfgModeReg

1857

//* \brief Configure the Mode Register of the ADC controller

1858

//*----------------------------------------------------------------------------

1859

static inline void

1860

AT91F_ADC_CfgModeReg (AT91PS_ADC pADC,	// pointer to a ADC controller

1861

		      unsigned int mode)	// mode register

1862

1863

  //* Write to the MR register

1864

  pADC->ADC_MR = mode;

1865

1866

1867

//*----------------------------------------------------------------------------

1868

//* \fn    AT91F_ADC_GetModeReg

1869

//* \brief Return the Mode Register of the ADC controller value

1870

//*----------------------------------------------------------------------------

1871

static inline unsigned int

1872

AT91F_ADC_GetModeReg (AT91PS_ADC pADC	// pointer to a ADC controller

1873

1874

1875

  return pADC->ADC_MR;

1876

1877

1878

//*----------------------------------------------------------------------------

1879

//* \fn    AT91F_ADC_CfgTimings

1880

//* \brief Configure the different necessary timings of the ADC controller

1881

//*----------------------------------------------------------------------------

1882

extern void AT91F_ADC_CfgTimings (AT91PS_ADC pADC,	// pointer to a ADC controller

1883

				  unsigned int mck_clock,	// in MHz

1884

				  unsigned int adc_clock,	// in MHz

1885

				  unsigned int startup_time,	// in us

1886

				  unsigned int sample_and_hold_time);	// in ns

1887

1888

//*----------------------------------------------------------------------------

1889

//* \fn    AT91F_ADC_EnableChannel

1890

//* \brief Return ADC Timer Register Value

1891

//*----------------------------------------------------------------------------

1892

static inline void

1893

AT91F_ADC_EnableChannel (AT91PS_ADC pADC,	// pointer to a ADC controller

1894

			 unsigned int channel)	// mode register

1895

1896

  //* Write to the CHER register

1897

  pADC->ADC_CHER = channel;

1898

1899

1900

//*----------------------------------------------------------------------------

1901

//* \fn    AT91F_ADC_DisableChannel

1902

//* \brief Return ADC Timer Register Value

1903

//*----------------------------------------------------------------------------

1904

static inline void

1905

AT91F_ADC_DisableChannel (AT91PS_ADC pADC,	// pointer to a ADC controller

1906

			  unsigned int channel)	// mode register

1907

1908

  //* Write to the CHDR register

1909

  pADC->ADC_CHDR = channel;

1910

1911

1912

//*----------------------------------------------------------------------------

1913

//* \fn    AT91F_ADC_GetChannelStatus

1914

//* \brief Return ADC Timer Register Value

1915

//*----------------------------------------------------------------------------

1916

static inline unsigned int

1917

AT91F_ADC_GetChannelStatus (AT91PS_ADC pADC	// pointer to a ADC controller

1918

1919

1920

  return pADC->ADC_CHSR;

1921

1922

1923

//*----------------------------------------------------------------------------

1924

//* \fn    AT91F_ADC_StartConversion

1925

//* \brief Software request for a analog to digital conversion

1926

//*----------------------------------------------------------------------------

1927

static inline void

1928

AT91F_ADC_StartConversion (AT91PS_ADC pADC	// pointer to a ADC controller

1929

1930

1931

  pADC->ADC_CR = AT91C_ADC_START;

1932

1933

1934

//*----------------------------------------------------------------------------

1935

//* \fn    AT91F_ADC_SoftReset

1936

//* \brief Software reset

1937

//*----------------------------------------------------------------------------

1938

static inline void

1939

AT91F_ADC_SoftReset (AT91PS_ADC pADC	// pointer to a ADC controller

1940

1941

1942

  pADC->ADC_CR = AT91C_ADC_SWRST;

1943

1944

1945

//*----------------------------------------------------------------------------

1946

//* \fn    AT91F_ADC_GetLastConvertedData

1947

//* \brief Return the Last Converted Data

1948

//*----------------------------------------------------------------------------

1949

static inline unsigned int

1950

AT91F_ADC_GetLastConvertedData (AT91PS_ADC pADC	// pointer to a ADC controller

1951

1952

1953

  return pADC->ADC_LCDR;

1954

1955

1956

//*----------------------------------------------------------------------------

1957

//* \fn    AT91F_ADC_GetConvertedDataCH0

1958

//* \brief Return the Channel 0 Converted Data

1959

//*----------------------------------------------------------------------------

1960

static inline unsigned int

1961

AT91F_ADC_GetConvertedDataCH0 (AT91PS_ADC pADC	// pointer to a ADC controller

1962

1963

1964

  return pADC->ADC_CDR0;

1965

1966

1967

//*----------------------------------------------------------------------------

1968

//* \fn    AT91F_ADC_GetConvertedDataCH1

1969

//* \brief Return the Channel 1 Converted Data

1970

//*----------------------------------------------------------------------------

1971

static inline unsigned int

1972

AT91F_ADC_GetConvertedDataCH1 (AT91PS_ADC pADC	// pointer to a ADC controller

1973

1974

1975

  return pADC->ADC_CDR1;

1976

1977

1978

//*----------------------------------------------------------------------------

1979

//* \fn    AT91F_ADC_GetConvertedDataCH2

1980

//* \brief Return the Channel 2 Converted Data

1981

//*----------------------------------------------------------------------------

1982

static inline unsigned int

1983

AT91F_ADC_GetConvertedDataCH2 (AT91PS_ADC pADC	// pointer to a ADC controller

1984

1985

1986

  return pADC->ADC_CDR2;

1987

1988

1989

//*----------------------------------------------------------------------------

1990

//* \fn    AT91F_ADC_GetConvertedDataCH3

1991

//* \brief Return the Channel 3 Converted Data

1992

//*----------------------------------------------------------------------------

1993

static inline unsigned int

1994

AT91F_ADC_GetConvertedDataCH3 (AT91PS_ADC pADC	// pointer to a ADC controller

1995

1996

1997

  return pADC->ADC_CDR3;

1998

1999

2000

//*----------------------------------------------------------------------------

2001

//* \fn    AT91F_ADC_GetConvertedDataCH4

2002

//* \brief Return the Channel 4 Converted Data

2003

//*----------------------------------------------------------------------------

2004

static inline unsigned int

2005

AT91F_ADC_GetConvertedDataCH4 (AT91PS_ADC pADC	// pointer to a ADC controller

2006

2007

2008

  return pADC->ADC_CDR4;

2009

2010

2011

//*----------------------------------------------------------------------------

2012

//* \fn    AT91F_ADC_GetConvertedDataCH5

2013

//* \brief Return the Channel 5 Converted Data

2014

//*----------------------------------------------------------------------------

2015

static inline unsigned int

2016

AT91F_ADC_GetConvertedDataCH5 (AT91PS_ADC pADC	// pointer to a ADC controller

2017

2018

2019

  return pADC->ADC_CDR5;

2020

2021

2022

//*----------------------------------------------------------------------------

2023

//* \fn    AT91F_ADC_GetConvertedDataCH6

2024

//* \brief Return the Channel 6 Converted Data

2025

//*----------------------------------------------------------------------------

2026

static inline unsigned int

2027

AT91F_ADC_GetConvertedDataCH6 (AT91PS_ADC pADC	// pointer to a ADC controller

2028

2029

2030

  return pADC->ADC_CDR6;

2031

2032

2033

//*----------------------------------------------------------------------------

2034

//* \fn    AT91F_ADC_GetConvertedDataCH7

2035

//* \brief Return the Channel 7 Converted Data

2036

//*----------------------------------------------------------------------------

2037

static inline unsigned int

2038

AT91F_ADC_GetConvertedDataCH7 (AT91PS_ADC pADC	// pointer to a ADC controller

2039

2040

2041

  return pADC->ADC_CDR7;

2042

2043

2044

/* *****************************************************************************

2045

                SOFTWARE API FOR SSC

2046

   ***************************************************************************** */

2047

//* Define the standard I2S mode configuration

2048

2049

//* Configuration to set in the SSC Transmit Clock Mode Register

2050

//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits

2051

//*                       nb_slot_by_frame : number of channels

2052

#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\

2053

									   AT91C_SSC_CKS_DIV   +\

2054

                            		   AT91C_SSC_CKO_CONTINOUS      +\

2055

                            		   AT91C_SSC_CKG_NONE    +\

2056

                                       AT91C_SSC_START_FALL_RF +\

2057

                           			   AT91C_SSC_STTOUT  +\

2058

                            		   ((1<<16) & AT91C_SSC_STTDLY) +\

2059

                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))

2060

2061

2062

//* Configuration to set in the SSC Transmit Frame Mode Register

2063

//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits

2064

//*                      nb_slot_by_frame : number of channels

2065

#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\

2066

									(nb_bit_by_slot-1)  +\

2067

                            		AT91C_SSC_MSBF   +\

2068

                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\

2069

                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\

2070

                            		AT91C_SSC_FSOS_NEGATIVE)

2071

2072

2073

//*----------------------------------------------------------------------------

2074

//* \fn    AT91F_SSC_SetBaudrate

2075

//* \brief Set the baudrate according to the CPU clock

2076

//*----------------------------------------------------------------------------

2077

extern void AT91F_SSC_SetBaudrate (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller

2078

				   unsigned int mainClock,	// \arg peripheral clock

2079

				   unsigned int speed);	// \arg SSC baudrate

2080

2081

//*----------------------------------------------------------------------------

2082

//* \fn    AT91F_SSC_Configure

2083

//* \brief Configure SSC

2084

//*----------------------------------------------------------------------------

2085

extern void AT91F_SSC_Configure (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller

2086

				 unsigned int syst_clock,	// \arg System Clock Frequency

2087

				 unsigned int baud_rate,	// \arg Expected Baud Rate Frequency

2088

				 unsigned int clock_rx,	// \arg Receiver Clock Parameters

2089

				 unsigned int mode_rx,	// \arg mode Register to be programmed

2090

				 unsigned int clock_tx,	// \arg Transmitter Clock Parameters

2091

				 unsigned int mode_tx);	// \arg mode Register to be programmed

2092

2093

//*----------------------------------------------------------------------------

2094

//* \fn    AT91F_SSC_EnableRx

2095

//* \brief Enable receiving datas

2096

//*----------------------------------------------------------------------------

2097

static inline void

2098

AT91F_SSC_EnableRx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller

2099

2100

  //* Enable receiver

2101

  pSSC->SSC_CR = AT91C_SSC_RXEN;

2102

2103

2104

//*----------------------------------------------------------------------------

2105

//* \fn    AT91F_SSC_DisableRx

2106

//* \brief Disable receiving datas

2107

//*----------------------------------------------------------------------------

2108

static inline void

2109

AT91F_SSC_DisableRx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller

2110

2111

  //* Disable receiver

2112

  pSSC->SSC_CR = AT91C_SSC_RXDIS;

2113

2114

2115

//*----------------------------------------------------------------------------

2116

//* \fn    AT91F_SSC_EnableTx

2117

//* \brief Enable sending datas

2118

//*----------------------------------------------------------------------------

2119

static inline void

2120

AT91F_SSC_EnableTx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller

2121

2122

  //* Enable  transmitter

2123

  pSSC->SSC_CR = AT91C_SSC_TXEN;

2124

2125

2126

//*----------------------------------------------------------------------------

2127

//* \fn    AT91F_SSC_DisableTx

2128

//* \brief Disable sending datas

2129

//*----------------------------------------------------------------------------

2130

static inline void

2131

AT91F_SSC_DisableTx (AT91PS_SSC pSSC)	// \arg pointer to a SSC controller

2132

2133

  //* Disable  transmitter

2134

  pSSC->SSC_CR = AT91C_SSC_TXDIS;

2135

2136

2137

//*----------------------------------------------------------------------------

2138

//* \fn    AT91F_SSC_EnableIt

2139

//* \brief Enable SSC IT

2140

//*----------------------------------------------------------------------------

2141

static inline void

2142

AT91F_SSC_EnableIt (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller

2143

		    unsigned int flag)	// \arg IT to be enabled

2144

2145

  //* Write to the IER register

2146

  pSSC->SSC_IER = flag;

2147

2148

2149

//*----------------------------------------------------------------------------

2150

//* \fn    AT91F_SSC_DisableIt

2151

//* \brief Disable SSC IT

2152

//*----------------------------------------------------------------------------

2153

static inline void

2154

AT91F_SSC_DisableIt (AT91PS_SSC pSSC,	// \arg pointer to a SSC controller

2155

		     unsigned int flag)	// \arg IT to be disabled

2156

2157

  //* Write to the IDR register

2158

  pSSC->SSC_IDR = flag;

2159

2160

2161

//*----------------------------------------------------------------------------

2162

//* \fn    AT91F_SSC_ReceiveFrame

2163

//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy

2164

//*----------------------------------------------------------------------------

2165

static inline unsigned int

2166

AT91F_SSC_ReceiveFrame (AT91PS_SSC pSSC,

2167

			unsigned char *pBuffer,

2168

			unsigned int szBuffer,

2169

			unsigned char *pNextBuffer, unsigned int szNextBuffer)

2170

2171

  return AT91F_PDC_ReceiveFrame ((AT91PS_PDC) & (pSSC->SSC_RPR),

2172

				 pBuffer,

2173

				 szBuffer, pNextBuffer, szNextBuffer);

2174

2175

2176

//*----------------------------------------------------------------------------

2177

//* \fn    AT91F_SSC_SendFrame

2178

//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy

2179

//*----------------------------------------------------------------------------

2180

static inline unsigned int

2181

AT91F_SSC_SendFrame (AT91PS_SSC pSSC,

2182

		     const unsigned char *pBuffer,

2183

		     unsigned int szBuffer,

2184

		     const unsigned char *pNextBuffer,

2185

		     unsigned int szNextBuffer)

2186

2187

  return AT91F_PDC_SendFrame ((AT91PS_PDC) & (pSSC->SSC_RPR),

2188

			      pBuffer, szBuffer, pNextBuffer, szNextBuffer);

2189

2190

2191

//*----------------------------------------------------------------------------

2192

//* \fn    AT91F_SSC_GetInterruptMaskStatus

2193

//* \brief Return SSC Interrupt Mask Status

2194

//*----------------------------------------------------------------------------

2195

static inline unsigned int

2196

AT91F_SSC_GetInterruptMaskStatus (	// \return SSC Interrupt Mask Status

2197

				   AT91PS_SSC pSsc)	// \arg  pointer to a SSC controller

2198

2199

  return pSsc->SSC_IMR;

2200

2201

2202

//*----------------------------------------------------------------------------

2203

//* \fn    AT91F_SSC_IsInterruptMasked

2204

//* \brief Test if SSC Interrupt is Masked

2205

//*----------------------------------------------------------------------------

2206

static inline int

2207

AT91F_SSC_IsInterruptMasked (AT91PS_SSC pSsc,	// \arg  pointer to a SSC controller

2208

			     unsigned int flag)	// \arg  flag to be tested

2209

2210

  return (AT91F_SSC_GetInterruptMaskStatus (pSsc) & flag);

2211

2212

2213

/* *****************************************************************************

2214

                SOFTWARE API FOR USART

2215

   ***************************************************************************** */

2216

//*----------------------------------------------------------------------------

2217

//* \fn    AT91F_US_Baudrate

2218

//* \brief Calculate the baudrate

2219

//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity

2220

#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \

2221

                        AT91C_US_NBSTOP_1_BIT + \

2222

                        AT91C_US_PAR_NONE + \

2223

                        AT91C_US_CHRL_8_BITS + \

2224

                        AT91C_US_CLKS_CLOCK )

2225

2226

//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity

2227

#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \

2228

                            AT91C_US_NBSTOP_1_BIT + \

2229

                            AT91C_US_PAR_NONE + \

2230

                            AT91C_US_CHRL_8_BITS + \

2231

                            AT91C_US_CLKS_EXT )

2232

2233

//* Standard Synchronous Mode : 8 bits , 1 stop , no parity

2234

#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \

2235

                       AT91C_US_USMODE_NORMAL + \

2236

                       AT91C_US_NBSTOP_1_BIT + \

2237

                       AT91C_US_PAR_NONE + \

2238

                       AT91C_US_CHRL_8_BITS + \

2239

                       AT91C_US_CLKS_CLOCK )

2240

2241

//* SCK used Label

2242

#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)

2243

2244

//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity

2245

#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \

2246

					   		 AT91C_US_CLKS_CLOCK +\

2247

                       		 AT91C_US_NBSTOP_1_BIT + \

2248

                       		 AT91C_US_PAR_EVEN + \

2249

                       		 AT91C_US_CHRL_8_BITS + \

2250

                       		 AT91C_US_CKLO +\

2251

                       		 AT91C_US_OVER)

2252

2253

//* Standard IRDA mode

2254

#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \

2255

                            AT91C_US_NBSTOP_1_BIT + \

2256

                            AT91C_US_PAR_NONE + \

2257

                            AT91C_US_CHRL_8_BITS + \

2258

                            AT91C_US_CLKS_CLOCK )

2259

2260

//*----------------------------------------------------------------------------

2261

//* \fn    AT91F_US_Baudrate

2262

//* \brief Caluculate baud_value according to the main clock and the baud rate

2263

//*----------------------------------------------------------------------------

2264

static inline unsigned int

2265

AT91F_US_Baudrate (const unsigned int main_clock,	// \arg peripheral clock

2266

		   const unsigned int baud_rate)	// \arg UART baudrate

2267

2268

  unsigned int baud_value = ((main_clock * 10) / (baud_rate * 16));

2269

  if ((baud_value % 10) >= 5)

2270

    baud_value = (baud_value / 10) + 1;

2271

  else

2272

    baud_value /= 10;

2273

  return baud_value;

2274

2275

2276

//*----------------------------------------------------------------------------

2277

//* \fn    AT91F_US_SetBaudrate

2278

//* \brief Set the baudrate according to the CPU clock

2279

//*----------------------------------------------------------------------------

2280

static inline void

2281

AT91F_US_SetBaudrate (AT91PS_USART pUSART,	// \arg pointer to a USART controller

2282

		      unsigned int mainClock,	// \arg peripheral clock

2283

		      unsigned int speed)	// \arg UART baudrate

2284

2285

  //* Define the baud rate divisor register

2286

  pUSART->US_BRGR = AT91F_US_Baudrate (mainClock, speed);

2287

2288

2289

//*----------------------------------------------------------------------------

2290

//* \fn    AT91F_US_SetTimeguard

2291

//* \brief Set USART timeguard

2292

//*----------------------------------------------------------------------------

2293

static inline void

2294

AT91F_US_SetTimeguard (AT91PS_USART pUSART,	// \arg pointer to a USART controller

2295

		       unsigned int timeguard)	// \arg timeguard value

2296

2297

  //* Write the Timeguard Register

2298

  pUSART->US_TTGR = timeguard;

2299

2300

2301

//*----------------------------------------------------------------------------

2302

//* \fn    AT91F_US_EnableIt

2303

//* \brief Enable USART IT

2304

//*----------------------------------------------------------------------------

2305

static inline void

2306

AT91F_US_EnableIt (AT91PS_USART pUSART,	// \arg pointer to a USART controller

2307

		   unsigned int flag)	// \arg IT to be enabled

2308

2309

  //* Write to the IER register

2310

  pUSART->US_IER = flag;

2311

2312

2313

//*----------------------------------------------------------------------------

2314

//* \fn    AT91F_US_DisableIt

2315

//* \brief Disable USART IT

2316

//*----------------------------------------------------------------------------

2317

static inline void

2318

AT91F_US_DisableIt (AT91PS_USART pUSART,	// \arg pointer to a USART controller

2319

		    unsigned int flag)	// \arg IT to be disabled

2320

2321

  //* Write to the IER register

2322

  pUSART->US_IDR = flag;

2323

2324

2325

//*----------------------------------------------------------------------------

2326

//* \fn    AT91F_US_Configure

2327

//* \brief Configure USART

2328

//*----------------------------------------------------------------------------

2329

extern void AT91F_US_Configure (AT91PS_USART pUSART,	// \arg pointer to a USART controller

2330

				unsigned int mainClock,	// \arg peripheral clock

2331

				unsigned int mode,	// \arg mode Register to be programmed

2332

				unsigned int baudRate,	// \arg baudrate to be programmed

2333

				unsigned int timeguard);	// \arg timeguard to be programmed

2334

2335

//*----------------------------------------------------------------------------

2336

//* \fn    AT91F_US_EnableRx

2337

//* \brief Enable receiving characters

2338

//*----------------------------------------------------------------------------

2339

static inline void

2340

AT91F_US_EnableRx (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2341

2342

  //* Enable receiver

2343

  pUSART->US_CR = AT91C_US_RXEN;

2344

2345

2346

//*----------------------------------------------------------------------------

2347

//* \fn    AT91F_US_EnableTx

2348

//* \brief Enable sending characters

2349

//*----------------------------------------------------------------------------

2350

static inline void

2351

AT91F_US_EnableTx (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2352

2353

  //* Enable  transmitter

2354

  pUSART->US_CR = AT91C_US_TXEN;

2355

2356

2357

//*----------------------------------------------------------------------------

2358

//* \fn    AT91F_US_ResetRx

2359

//* \brief Reset Receiver and re-enable it

2360

//*----------------------------------------------------------------------------

2361

static inline void

2362

AT91F_US_ResetRx (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2363

2364

  //* Reset receiver

2365

  pUSART->US_CR = AT91C_US_RSTRX;

2366

  //* Re-Enable receiver

2367

  pUSART->US_CR = AT91C_US_RXEN;

2368

2369

2370

//*----------------------------------------------------------------------------

2371

//* \fn    AT91F_US_ResetTx

2372

//* \brief Reset Transmitter and re-enable it

2373

//*----------------------------------------------------------------------------

2374

static inline void

2375

AT91F_US_ResetTx (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2376

2377

  //* Reset transmitter

2378

  pUSART->US_CR = AT91C_US_RSTTX;

2379

  //* Enable transmitter

2380

  pUSART->US_CR = AT91C_US_TXEN;

2381

2382

2383

//*----------------------------------------------------------------------------

2384

//* \fn    AT91F_US_DisableRx

2385

//* \brief Disable Receiver

2386

//*----------------------------------------------------------------------------

2387

static inline void

2388

AT91F_US_DisableRx (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2389

2390

  //* Disable receiver

2391

  pUSART->US_CR = AT91C_US_RXDIS;

2392

2393

2394

//*----------------------------------------------------------------------------

2395

//* \fn    AT91F_US_DisableTx

2396

//* \brief Disable Transmitter

2397

//*----------------------------------------------------------------------------

2398

static inline void

2399

AT91F_US_DisableTx (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2400

2401

  //* Disable transmitter

2402

  pUSART->US_CR = AT91C_US_TXDIS;

2403

2404

2405

//*----------------------------------------------------------------------------

2406

//* \fn    AT91F_US_Close

2407

//* \brief Close USART: disable IT disable receiver and transmitter, close PDC

2408

//*----------------------------------------------------------------------------

2409

extern void AT91F_US_Close (AT91PS_USART pUSART);	// \arg pointer to a USART controller

2410

2411

//*----------------------------------------------------------------------------

2412

//* \fn    AT91F_US_TxReady

2413

//* \brief Return 1 if a character can be written in US_THR

2414

//*----------------------------------------------------------------------------

2415

static inline unsigned int

2416

AT91F_US_TxReady (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2417

2418

  return (pUSART->US_CSR & AT91C_US_TXRDY);

2419

2420

2421

//*----------------------------------------------------------------------------

2422

//* \fn    AT91F_US_RxReady

2423

//* \brief Return 1 if a character can be read in US_RHR

2424

//*----------------------------------------------------------------------------

2425

static inline unsigned int

2426

AT91F_US_RxReady (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2427

2428

  return (pUSART->US_CSR & AT91C_US_RXRDY);

2429

2430

2431

//*----------------------------------------------------------------------------

2432

//* \fn    AT91F_US_Error

2433

//* \brief Return the error flag

2434

//*----------------------------------------------------------------------------

2435

static inline unsigned int

2436

AT91F_US_Error (AT91PS_USART pUSART)	// \arg pointer to a USART controller

2437

2438

  return (pUSART->US_CSR & (AT91C_US_OVRE |	// Overrun error

2439

			    AT91C_US_FRAME |	// Framing error

2440

			    AT91C_US_PARE));	// Parity error

2441

2442

2443

//*----------------------------------------------------------------------------

2444

//* \fn    AT91F_US_PutChar

2445

//* \brief Send a character,does not check if ready to send

2446

//*----------------------------------------------------------------------------

2447

static inline void

2448

AT91F_US_PutChar (AT91PS_USART pUSART, int character)

2449

2450

  pUSART->US_THR = (character & 0x1FF);

2451

2452

2453

//*----------------------------------------------------------------------------

2454

//* \fn    AT91F_US_GetChar

2455

//* \brief Receive a character,does not check if a character is available

2456

//*----------------------------------------------------------------------------

2457

static inline int

2458

AT91F_US_GetChar (const AT91PS_USART pUSART)

2459

2460

  return ((pUSART->US_RHR) & 0x1FF);

2461

2462

2463

//*----------------------------------------------------------------------------

2464

//* \fn    AT91F_US_SendFrame

2465

//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy

2466

//*----------------------------------------------------------------------------

2467

static inline unsigned int

2468

AT91F_US_SendFrame (AT91PS_USART pUSART,

2469

		    const unsigned char *pBuffer,

2470

		    unsigned int szBuffer,

2471

		    const unsigned char *pNextBuffer,

2472

		    unsigned int szNextBuffer)

2473

2474

  return AT91F_PDC_SendFrame ((AT91PS_PDC) & (pUSART->US_RPR),

2475

			      pBuffer, szBuffer, pNextBuffer, szNextBuffer);

2476

2477

2478

//*----------------------------------------------------------------------------

2479

//* \fn    AT91F_US_ReceiveFrame

2480

//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy

2481

//*----------------------------------------------------------------------------

2482

static inline unsigned int

2483

AT91F_US_ReceiveFrame (AT91PS_USART pUSART,

2484

		       unsigned char *pBuffer,

2485

		       unsigned int szBuffer,

2486

		       unsigned char *pNextBuffer, unsigned int szNextBuffer)

2487

2488

  return AT91F_PDC_ReceiveFrame ((AT91PS_PDC) & (pUSART->US_RPR),

2489

				 pBuffer,

2490

				 szBuffer, pNextBuffer, szNextBuffer);

2491

2492

2493

//*----------------------------------------------------------------------------

2494

//* \fn    AT91F_US_SetIrdaFilter

2495

//* \brief Set the value of IrDa filter tregister

2496

//*----------------------------------------------------------------------------

2497

static inline void

2498

AT91F_US_SetIrdaFilter (AT91PS_USART pUSART, unsigned char value)

2499

2500

  pUSART->US_IF = value;

2501

2502

2503

/* *****************************************************************************

2504

                SOFTWARE API FOR TWI

2505

   ***************************************************************************** */

2506

//*----------------------------------------------------------------------------

2507

//* \fn    AT91F_TWI_EnableIt

2508

//* \brief Enable TWI IT

2509

//*----------------------------------------------------------------------------

2510

static inline void

2511

AT91F_TWI_EnableIt (AT91PS_TWI pTWI,	// \arg pointer to a TWI controller

2512

		    unsigned int flag)	// \arg IT to be enabled

2513

2514

  //* Write to the IER register

2515

  pTWI->TWI_IER = flag;

2516

2517

2518

//*----------------------------------------------------------------------------

2519

//* \fn    AT91F_TWI_DisableIt

2520

//* \brief Disable TWI IT

2521

//*----------------------------------------------------------------------------

2522

static inline void

2523

AT91F_TWI_DisableIt (AT91PS_TWI pTWI,	// \arg pointer to a TWI controller

2524

		     unsigned int flag)	// \arg IT to be disabled

2525

2526

  //* Write to the IDR register

2527

  pTWI->TWI_IDR = flag;

2528

2529

2530

//*----------------------------------------------------------------------------

2531

//* \fn    AT91F_TWI_Configure

2532

//* \brief Configure TWI in master mode

2533

//*----------------------------------------------------------------------------

2534

static inline void

2535

AT91F_TWI_Configure (AT91PS_TWI pTWI)	// \arg pointer to a TWI controller

2536

2537

  //* Disable interrupts

2538

  pTWI->TWI_IDR = (unsigned int) -1;

2539

2540

  //* Reset peripheral

2541

  pTWI->TWI_CR = AT91C_TWI_SWRST;

2542

2543

  //* Set Master mode

2544

  pTWI->TWI_CR = AT91C_TWI_MSEN;

//*----------------------------------------------------------------------------

2549

//* \fn    AT91F_TWI_GetInterruptMaskStatus

2550

//* \brief Return TWI Interrupt Mask Status

2551

//*----------------------------------------------------------------------------

2552

static inline unsigned int

2553

AT91F_TWI_GetInterruptMaskStatus (	// \return TWI Interrupt Mask Status

2554

				   AT91PS_TWI pTwi)	// \arg  pointer to a TWI controller

2555

2556

  return pTwi->TWI_IMR;

2557

2558

2559

//*----------------------------------------------------------------------------

2560

//* \fn    AT91F_TWI_IsInterruptMasked

2561

//* \brief Test if TWI Interrupt is Masked

2562

//*----------------------------------------------------------------------------

2563

static inline int

2564

AT91F_TWI_IsInterruptMasked (AT91PS_TWI pTwi,	// \arg  pointer to a TWI controller

2565

			     unsigned int flag)	// \arg  flag to be tested

2566

2567

  return (AT91F_TWI_GetInterruptMaskStatus (pTwi) & flag);

2568

2569

2570

/* *****************************************************************************

2571

                SOFTWARE API FOR TC

2572

   ***************************************************************************** */

2573

//*----------------------------------------------------------------------------

2574

//* \fn    AT91F_TC_InterruptEnable

2575

//* \brief Enable TC Interrupt

2576

//*----------------------------------------------------------------------------

2577

static inline void

2578

AT91F_TC_InterruptEnable (AT91PS_TC pTc,	// \arg  pointer to a TC controller

2579

			  unsigned int flag)	// \arg  TC interrupt to be enabled

2580

2581

  pTc->TC_IER = flag;

2582

2583

2584

//*----------------------------------------------------------------------------

2585

//* \fn    AT91F_TC_InterruptDisable

2586

//* \brief Disable TC Interrupt

2587

//*----------------------------------------------------------------------------

2588

static inline void

2589

AT91F_TC_InterruptDisable (AT91PS_TC pTc,	// \arg  pointer to a TC controller

2590

			   unsigned int flag)	// \arg  TC interrupt to be disabled

2591

2592

  pTc->TC_IDR = flag;

2593

2594

2595

//*----------------------------------------------------------------------------

2596

//* \fn    AT91F_TC_GetInterruptMaskStatus

2597

//* \brief Return TC Interrupt Mask Status

2598

//*----------------------------------------------------------------------------

2599

static inline unsigned int

2600

AT91F_TC_GetInterruptMaskStatus (	// \return TC Interrupt Mask Status

2601

				  AT91PS_TC pTc)	// \arg  pointer to a TC controller

2602

2603

  return pTc->TC_IMR;

2604

2605

2606

//*----------------------------------------------------------------------------

2607

//* \fn    AT91F_TC_IsInterruptMasked

2608

//* \brief Test if TC Interrupt is Masked

2609

//*----------------------------------------------------------------------------

2610

static inline int

2611

AT91F_TC_IsInterruptMasked (AT91PS_TC pTc,	// \arg  pointer to a TC controller

2612

			    unsigned int flag)	// \arg  flag to be tested

2613

2614

  return (AT91F_TC_GetInterruptMaskStatus (pTc) & flag);

2615

2616

2617

/* *****************************************************************************

2618

                SOFTWARE API FOR PWMC

2619

   ***************************************************************************** */

2620

//*----------------------------------------------------------------------------

2621

//* \fn    AT91F_PWM_GetStatus

2622

//* \brief Return PWM Interrupt Status

2623

//*----------------------------------------------------------------------------

2624

static inline unsigned int

2625

AT91F_PWMC_GetStatus (		// \return PWM Interrupt Status

2626

		       AT91PS_PWMC pPWM)	// pointer to a PWM controller

2627

2628

  return pPWM->PWMC_SR;

2629

2630

2631

//*----------------------------------------------------------------------------

2632

//* \fn    AT91F_PWM_InterruptEnable

2633

//* \brief Enable PWM Interrupt

2634

//*----------------------------------------------------------------------------

2635

static inline void

2636

AT91F_PWMC_InterruptEnable (AT91PS_PWMC pPwm,	// \arg  pointer to a PWM controller

2637

			    unsigned int flag)	// \arg  PWM interrupt to be enabled

2638

2639

  pPwm->PWMC_IER = flag;

2640

2641

2642

//*----------------------------------------------------------------------------

2643

//* \fn    AT91F_PWM_InterruptDisable

2644

//* \brief Disable PWM Interrupt

2645

//*----------------------------------------------------------------------------

2646

static inline void

2647

AT91F_PWMC_InterruptDisable (AT91PS_PWMC pPwm,	// \arg  pointer to a PWM controller

2648

			     unsigned int flag)	// \arg  PWM interrupt to be disabled

2649

2650

  pPwm->PWMC_IDR = flag;

2651

2652

2653

//*----------------------------------------------------------------------------

2654

//* \fn    AT91F_PWM_GetInterruptMaskStatus

2655

//* \brief Return PWM Interrupt Mask Status

2656

//*----------------------------------------------------------------------------

2657

static inline unsigned int

2658

AT91F_PWMC_GetInterruptMaskStatus (	// \return PWM Interrupt Mask Status

2659

				    AT91PS_PWMC pPwm)	// \arg  pointer to a PWM controller

2660

2661

  return pPwm->PWMC_IMR;

2662

2663

2664

//*----------------------------------------------------------------------------

2665

//* \fn    AT91F_PWM_IsInterruptMasked

2666

//* \brief Test if PWM Interrupt is Masked

2667

//*----------------------------------------------------------------------------

2668

static inline unsigned int

2669

AT91F_PWMC_IsInterruptMasked (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller

2670

			      unsigned int flag)	// \arg  flag to be tested

2671

2672

  return (AT91F_PWMC_GetInterruptMaskStatus (pPWM) & flag);

2673

2674

2675

//*----------------------------------------------------------------------------

2676

//* \fn    AT91F_PWM_IsStatusSet

2677

//* \brief Test if PWM Interrupt is Set

2678

//*----------------------------------------------------------------------------

2679

static inline unsigned int

2680

AT91F_PWMC_IsStatusSet (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller

2681

			unsigned int flag)	// \arg  flag to be tested

2682

2683

  return (AT91F_PWMC_GetStatus (pPWM) & flag);

2684

2685

2686

//*----------------------------------------------------------------------------

2687

//* \fn    AT91F_PWM_CfgChannel

2688

//* \brief Test if PWM Interrupt is Set

2689

//*----------------------------------------------------------------------------

2690

static inline void

2691

AT91F_PWMC_CfgChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller

2692

		       unsigned int channelId,	// \arg PWM channel ID

2693

		       unsigned int mode,	// \arg  PWM mode

2694

		       unsigned int period,	// \arg PWM period

2695

		       unsigned int duty)	// \arg PWM duty cycle

2696

2697

  pPWM->PWMC_CH[channelId].PWMC_CMR = mode;

2698

  pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;

2699

  pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;

2700

2701

2702

//*----------------------------------------------------------------------------

2703

//* \fn    AT91F_PWM_StartChannel

2704

//* \brief Enable channel

2705

//*----------------------------------------------------------------------------

2706

static inline void

2707

AT91F_PWMC_StartChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller

2708

			 unsigned int flag)	// \arg  Channels IDs to be enabled

2709

2710

  pPWM->PWMC_ENA = flag;

2711

2712

2713

//*----------------------------------------------------------------------------

2714

//* \fn    AT91F_PWM_StopChannel

2715

//* \brief Disable channel

2716

//*----------------------------------------------------------------------------

2717

static inline void

2718

AT91F_PWMC_StopChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller

2719

			unsigned int flag)	// \arg  Channels IDs to be enabled

2720

2721

  pPWM->PWMC_DIS = flag;

2722

2723

2724

//*----------------------------------------------------------------------------

2725

//* \fn    AT91F_PWM_UpdateChannel

2726

//* \brief Update Period or Duty Cycle

2727

//*----------------------------------------------------------------------------

2728

static inline void

2729

AT91F_PWMC_UpdateChannel (AT91PS_PWMC pPWM,	// \arg  pointer to a PWM controller

2730

			  unsigned int channelId,	// \arg PWM channel ID

2731

			  unsigned int update)	// \arg  Channels IDs to be enabled

2732

2733

  pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;

2734

2735

2736

/* *****************************************************************************

2737

                SOFTWARE API FOR UDP

2738

   ***************************************************************************** */

2739

//*----------------------------------------------------------------------------

2740

//* \fn    AT91F_UDP_EnableIt

2741

//* \brief Enable UDP IT

2742

//*----------------------------------------------------------------------------

2743

static inline void

2744

AT91F_UDP_EnableIt (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2745

		    unsigned int flag)	// \arg IT to be enabled

2746

2747

  //* Write to the IER register

2748

  pUDP->UDP_IER = flag;

2749

2750

2751

//*----------------------------------------------------------------------------

2752

//* \fn    AT91F_UDP_DisableIt

2753

//* \brief Disable UDP IT

2754

//*----------------------------------------------------------------------------

2755

static inline void

2756

AT91F_UDP_DisableIt (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2757

		     unsigned int flag)	// \arg IT to be disabled

2758

2759

  //* Write to the IDR register

2760

  pUDP->UDP_IDR = flag;

2761

2762

2763

//*----------------------------------------------------------------------------

2764

//* \fn    AT91F_UDP_SetAddress

2765

//* \brief Set UDP functional address

2766

//*----------------------------------------------------------------------------

2767

static inline void

2768

AT91F_UDP_SetAddress (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2769

		      unsigned char address)	// \arg new UDP address

2770

2771

  pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);

2772

2773

2774

//*----------------------------------------------------------------------------

2775

//* \fn    AT91F_UDP_EnableEp

2776

//* \brief Enable Endpoint

2777

//*----------------------------------------------------------------------------

2778

static inline void

2779

AT91F_UDP_EnableEp (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2780

		    unsigned char endpoint)	// \arg endpoint number

2781

2782

  pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;

2783

2784

2785

//*----------------------------------------------------------------------------

2786

//* \fn    AT91F_UDP_DisableEp

2787

//* \brief Enable Endpoint

2788

//*----------------------------------------------------------------------------

2789

static inline void

2790

AT91F_UDP_DisableEp (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2791

		     unsigned char endpoint)	// \arg endpoint number

2792

2793

  pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;

2794

2795

2796

//*----------------------------------------------------------------------------

2797

//* \fn    AT91F_UDP_SetState

2798

//* \brief Set UDP Device state

2799

//*----------------------------------------------------------------------------

2800

static inline void

2801

AT91F_UDP_SetState (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2802

		    unsigned int flag)	// \arg new UDP address

2803

2804

  pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);

2805

  pUDP->UDP_GLBSTATE |= flag;

2806

2807

2808

//*----------------------------------------------------------------------------

2809

//* \fn    AT91F_UDP_GetState

2810

//* \brief return UDP Device state

2811

//*----------------------------------------------------------------------------

2812

static inline unsigned int

2813

AT91F_UDP_GetState (		// \return the UDP device state

2814

		     AT91PS_UDP pUDP)	// \arg pointer to a UDP controller

2815

2816

  return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));

2817

2818

2819

//*----------------------------------------------------------------------------

2820

//* \fn    AT91F_UDP_ResetEp

2821

//* \brief Reset UDP endpoint

2822

//*----------------------------------------------------------------------------

2823

static inline void

2824

AT91F_UDP_ResetEp (		// \return the UDP device state

2825

		    AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2826

		    unsigned int flag)	// \arg Endpoints to be reset

2827

2828

  pUDP->UDP_RSTEP = flag;

2829

  pUDP->UDP_RSTEP = 0;

2830

2831

2832

//*----------------------------------------------------------------------------

2833

//* \fn    AT91F_UDP_EpStall

2834

//* \brief Endpoint will STALL requests

2835

//*----------------------------------------------------------------------------

2836

static inline void

2837

AT91F_UDP_EpStall (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2838

		   unsigned char endpoint)	// \arg endpoint number

2839

2840

  pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;

2841

2842

2843

//*----------------------------------------------------------------------------

2844

//* \fn    AT91F_UDP_EpWrite

2845

//* \brief Write value in the DPR

2846

//*----------------------------------------------------------------------------

2847

static inline void

2848

AT91F_UDP_EpWrite (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2849

		   unsigned char endpoint,	// \arg endpoint number

2850

		   unsigned char value)	// \arg value to be written in the DPR

2851

2852

  pUDP->UDP_FDR[endpoint] = value;

2853

2854

2855

//*----------------------------------------------------------------------------

2856

//* \fn    AT91F_UDP_EpRead

2857

//* \brief Return value from the DPR

2858

//*----------------------------------------------------------------------------

2859

static inline unsigned int

2860

AT91F_UDP_EpRead (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2861

		  unsigned char endpoint)	// \arg endpoint number

2862

2863

  return pUDP->UDP_FDR[endpoint];

2864

2865

2866

//*----------------------------------------------------------------------------

2867

//* \fn    AT91F_UDP_EpEndOfWr

2868

//* \brief Notify the UDP that values in DPR are ready to be sent

2869

//*----------------------------------------------------------------------------

2870

static inline void

2871

AT91F_UDP_EpEndOfWr (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2872

		     unsigned char endpoint)	// \arg endpoint number

2873

2874

  pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;

2875

2876

2877

//*----------------------------------------------------------------------------

2878

//* \fn    AT91F_UDP_EpClear

2879

//* \brief Clear flag in the endpoint CSR register

2880

//*----------------------------------------------------------------------------

2881

static inline void

2882

AT91F_UDP_EpClear (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2883

		   unsigned char endpoint,	// \arg endpoint number

2884

		   unsigned int flag)	// \arg flag to be cleared

2885

2886

  pUDP->UDP_CSR[endpoint] &= ~(flag);

2887

2888

2889

//*----------------------------------------------------------------------------

2890

//* \fn    AT91F_UDP_EpSet

2891

//* \brief Set flag in the endpoint CSR register

2892

//*----------------------------------------------------------------------------

2893

static inline void

2894

AT91F_UDP_EpSet (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2895

		 unsigned char endpoint,	// \arg endpoint number

2896

		 unsigned int flag)	// \arg flag to be cleared

2897

2898

  pUDP->UDP_CSR[endpoint] |= flag;

2899

2900

2901

//*----------------------------------------------------------------------------

2902

//* \fn    AT91F_UDP_EpStatus

2903

//* \brief Return the endpoint CSR register

2904

//*----------------------------------------------------------------------------

2905

static inline unsigned int

2906

AT91F_UDP_EpStatus (AT91PS_UDP pUDP,	// \arg pointer to a UDP controller

2907

		    unsigned char endpoint)	// \arg endpoint number

2908

2909

  return pUDP->UDP_CSR[endpoint];

2910

2911

2912

//*----------------------------------------------------------------------------

2913

//* \fn    AT91F_UDP_GetInterruptMaskStatus

2914

//* \brief Return UDP Interrupt Mask Status

2915

//*----------------------------------------------------------------------------

2916

static inline unsigned int

2917

AT91F_UDP_GetInterruptMaskStatus (AT91PS_UDP pUdp)	// \arg  pointer to a UDP controller

2918

2919

  return pUdp->UDP_IMR;

2920

2921

2922

//*----------------------------------------------------------------------------

2923

//* \fn    AT91F_UDP_IsInterruptMasked

2924

//* \brief Test if UDP Interrupt is Masked

2925

//*----------------------------------------------------------------------------

2926

static inline int

2927

AT91F_UDP_IsInterruptMasked (AT91PS_UDP pUdp,	// \arg  pointer to a UDP controller

2928

			     unsigned int flag)	// \arg  flag to be tested

2929

2930

  return (AT91F_UDP_GetInterruptMaskStatus (pUdp) & flag);

2931

2932

2933

// ----------------------------------------------------------------------------

2934

//  \fn    AT91F_UDP_InterruptStatusRegister

2935

//  \brief Return the Interrupt Status Register

2936

// ----------------------------------------------------------------------------

2937

static inline unsigned int

2938

AT91F_UDP_InterruptStatusRegister (AT91PS_UDP pUDP)	// \arg  pointer to a UDP controller

2939

2940

  return pUDP->UDP_ISR;

2941

2942

2943

// ----------------------------------------------------------------------------

2944

//  \fn    AT91F_UDP_InterruptClearRegister

2945

//  \brief Clear Interrupt Register

2946

// ----------------------------------------------------------------------------

2947

static inline void

2948

AT91F_UDP_InterruptClearRegister (AT91PS_UDP pUDP,	// \arg pointer to UDP controller

2949

				  unsigned int flag)	// \arg IT to be cleat

2950

2951

  pUDP->UDP_ICR = flag;

2952

2953

2954

// ----------------------------------------------------------------------------

2955

//  \fn    AT91F_UDP_EnableTransceiver

2956

//  \brief Enable transceiver

2957

// ----------------------------------------------------------------------------

2958

static inline void

2959

AT91F_UDP_EnableTransceiver (AT91PS_UDP pUDP)	// \arg  pointer to a UDP controller

2960

2961

  pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS;

2962

2963

2964

// ----------------------------------------------------------------------------

2965

//  \fn    AT91F_UDP_DisableTransceiver

2966

//  \brief Disable transceiver

2967

// ----------------------------------------------------------------------------

2968

static inline void

2969

AT91F_UDP_DisableTransceiver (AT91PS_UDP pUDP)	// \arg  pointer to a UDP controller

2970

2971

  pUDP->UDP_TXVC = AT91C_UDP_TXVDIS;

2972

2973

2974

//*----------------------------------------------------------------------------

2975

//* \fn    AT91F_DBGU_CfgPMC

2976

//* \brief Enable Peripheral clock in PMC for  DBGU

2977

//*----------------------------------------------------------------------------

2978

static inline void

2979

AT91F_DBGU_CfgPMC (void)

2980

2981

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

2982

			       ((unsigned int) 1 << AT91C_ID_SYS));

2983

2984

2985

//*----------------------------------------------------------------------------

2986

//* \fn    AT91F_DBGU_CfgPIO

2987

//* \brief Configure PIO controllers to drive DBGU signals

2988

//*----------------------------------------------------------------------------

2989

static inline void

2990

AT91F_DBGU_CfgPIO (void)

2991

2992

  // Configure PIO controllers to periph mode

2993

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

2994

		       ((unsigned int) AT91C_PA9_DRXD) | ((unsigned int) AT91C_PA10_DTXD),	// Peripheral A

2995

		       0);	// Peripheral B

2996

2997

2998

//*----------------------------------------------------------------------------

2999

//* \fn    AT91F_PMC_CfgPMC

3000

//* \brief Enable Peripheral clock in PMC for  PMC

3001

//*----------------------------------------------------------------------------

3002

static inline void

3003

AT91F_PMC_CfgPMC (void)

3004

3005

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3006

			       ((unsigned int) 1 << AT91C_ID_SYS));

3007

3008

3009

//*----------------------------------------------------------------------------

3010

//* \fn    AT91F_PMC_CfgPIO

3011

//* \brief Configure PIO controllers to drive PMC signals

3012

//*----------------------------------------------------------------------------

3013

static inline void

3014

AT91F_PMC_CfgPIO (void)

3015

3016

  // Configure PIO controllers to periph mode

3017

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3018

		       0,	// Peripheral A

3019

		       ((unsigned int) AT91C_PA6_PCK0) | ((unsigned int) AT91C_PA18_PCK2) | ((unsigned int) AT91C_PA31_PCK2) | ((unsigned int) AT91C_PA21_PCK1) | ((unsigned int) AT91C_PA17_PCK1));	// Peripheral B

3020

3021

3022

//*----------------------------------------------------------------------------

3023

//* \fn    AT91F_VREG_CfgPMC

3024

//* \brief Enable Peripheral clock in PMC for  VREG

3025

//*----------------------------------------------------------------------------

3026

static inline void

3027

AT91F_VREG_CfgPMC (void)

3028

3029

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3030

			       ((unsigned int) 1 << AT91C_ID_SYS));

3031

3032

3033

//*----------------------------------------------------------------------------

3034

//* \fn    AT91F_RSTC_CfgPMC

3035

//* \brief Enable Peripheral clock in PMC for  RSTC

3036

//*----------------------------------------------------------------------------

3037

static inline void

3038

AT91F_RSTC_CfgPMC (void)

3039

3040

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3041

			       ((unsigned int) 1 << AT91C_ID_SYS));

3042

3043

3044

//*----------------------------------------------------------------------------

3045

//* \fn    AT91F_SSC_CfgPMC

3046

//* \brief Enable Peripheral clock in PMC for  SSC

3047

//*----------------------------------------------------------------------------

3048

static inline void

3049

AT91F_SSC_CfgPMC (void)

3050

3051

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3052

			       ((unsigned int) 1 << AT91C_ID_SSC));

3053

3054

3055

//*----------------------------------------------------------------------------

3056

//* \fn    AT91F_SSC_CfgPIO

3057

//* \brief Configure PIO controllers to drive SSC signals

3058

//*----------------------------------------------------------------------------

3059

static inline void

3060

AT91F_SSC_CfgPIO (void)

3061

3062

  // Configure PIO controllers to periph mode

3063

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3064

		       ((unsigned int) AT91C_PA19_RK) | ((unsigned int) AT91C_PA16_TK) | ((unsigned int) AT91C_PA15_TF) | ((unsigned int) AT91C_PA18_RD) | ((unsigned int) AT91C_PA20_RF) | ((unsigned int) AT91C_PA17_TD),	// Peripheral A

3065

		       0);	// Peripheral B

3066

3067

3068

//*----------------------------------------------------------------------------

3069

//* \fn    AT91F_WDTC_CfgPMC

3070

//* \brief Enable Peripheral clock in PMC for  WDTC

3071

//*----------------------------------------------------------------------------

3072

static inline void

3073

AT91F_WDTC_CfgPMC (void)

3074

3075

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3076

			       ((unsigned int) 1 << AT91C_ID_SYS));

3077

3078

3079

//*----------------------------------------------------------------------------

3080

//* \fn    AT91F_US1_CfgPMC

3081

//* \brief Enable Peripheral clock in PMC for  US1

3082

//*----------------------------------------------------------------------------

3083

static inline void

3084

AT91F_US1_CfgPMC (void)

3085

3086

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3087

			       ((unsigned int) 1 << AT91C_ID_US1));

3088

3089

3090

//*----------------------------------------------------------------------------

3091

//* \fn    AT91F_US1_CfgPIO

3092

//* \brief Configure PIO controllers to drive US1 signals

3093

//*----------------------------------------------------------------------------

3094

static inline void

3095

AT91F_US1_CfgPIO (void)

3096

3097

  // Configure PIO controllers to periph mode

3098

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3099

		       ((unsigned int) AT91C_PA29_RI1) | ((unsigned int) AT91C_PA26_DCD1) | ((unsigned int) AT91C_PA28_DSR1) | ((unsigned int) AT91C_PA27_DTR1) | ((unsigned int) AT91C_PA23_SCK1) | ((unsigned int) AT91C_PA24_RTS1) | ((unsigned int) AT91C_PA22_TXD1) | ((unsigned int) AT91C_PA21_RXD1) | ((unsigned int) AT91C_PA25_CTS1),	// Peripheral A

3100

		       0);	// Peripheral B

3101

3102

3103

//*----------------------------------------------------------------------------

3104

//* \fn    AT91F_US0_CfgPMC

3105

//* \brief Enable Peripheral clock in PMC for  US0

3106

//*----------------------------------------------------------------------------

3107

static inline void

3108

AT91F_US0_CfgPMC (void)

3109

3110

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3111

			       ((unsigned int) 1 << AT91C_ID_US0));

3112

3113

3114

//*----------------------------------------------------------------------------

3115

//* \fn    AT91F_US0_CfgPIO

3116

//* \brief Configure PIO controllers to drive US0 signals

3117

//*----------------------------------------------------------------------------

3118

static inline void

3119

AT91F_US0_CfgPIO (void)

3120

3121

  // Configure PIO controllers to periph mode

3122

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3123

		       ((unsigned int) AT91C_PA5_RXD0) | ((unsigned int) AT91C_PA8_CTS0) | ((unsigned int) AT91C_PA7_RTS0) | ((unsigned int) AT91C_PA6_TXD0),	// Peripheral A

3124

		       ((unsigned int) AT91C_PA2_SCK0));	// Peripheral B

3125

3126

3127

//*----------------------------------------------------------------------------

3128

//* \fn    AT91F_SPI_CfgPMC

3129

//* \brief Enable Peripheral clock in PMC for  SPI

3130

//*----------------------------------------------------------------------------

3131

static inline void

3132

AT91F_SPI_CfgPMC (void)

3133

3134

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3135

			       ((unsigned int) 1 << AT91C_ID_SPI));

3136

3137

3138

//*----------------------------------------------------------------------------

3139

//* \fn    AT91F_SPI_CfgPIO

3140

//* \brief Configure PIO controllers to drive SPI signals

3141

//*----------------------------------------------------------------------------

3142

static inline void

3143

AT91F_SPI_CfgPIO (void)

3144

3145

  // Configure PIO controllers to periph mode

3146

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3147

		       ((unsigned int) AT91C_PA13_MOSI) | ((unsigned int) AT91C_PA31_NPCS1) | ((unsigned int) AT91C_PA14_SPCK) | ((unsigned int) AT91C_PA11_NPCS0) | ((unsigned int) AT91C_PA12_MISO),	// Peripheral A

3148

		       ((unsigned int) AT91C_PA9_NPCS1) | ((unsigned int) AT91C_PA22_NPCS3) | ((unsigned int) AT91C_PA3_NPCS3) | ((unsigned int) AT91C_PA5_NPCS3) | ((unsigned int) AT91C_PA10_NPCS2) | ((unsigned int) AT91C_PA30_NPCS2));	// Peripheral B

3149

3150

3151

//*----------------------------------------------------------------------------

3152

//* \fn    AT91F_PITC_CfgPMC

3153

//* \brief Enable Peripheral clock in PMC for  PITC

3154

//*----------------------------------------------------------------------------

3155

static inline void

3156

AT91F_PITC_CfgPMC (void)

3157

3158

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3159

			       ((unsigned int) 1 << AT91C_ID_SYS));

3160

3161

3162

//*----------------------------------------------------------------------------

3163

//* \fn    AT91F_AIC_CfgPMC

3164

//* \brief Enable Peripheral clock in PMC for  AIC

3165

//*----------------------------------------------------------------------------

3166

static inline void

3167

AT91F_AIC_CfgPMC (void)

3168

3169

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3170

			       ((unsigned int) 1 << AT91C_ID_FIQ) |

3171

			       ((unsigned int) 1 << AT91C_ID_IRQ0) |

3172

			       ((unsigned int) 1 << AT91C_ID_IRQ1));

3173

3174

3175

//*----------------------------------------------------------------------------

3176

//* \fn    AT91F_AIC_CfgPIO

3177

//* \brief Configure PIO controllers to drive AIC signals

3178

//*----------------------------------------------------------------------------

3179

static inline void

3180

AT91F_AIC_CfgPIO (void)

3181

3182

  // Configure PIO controllers to periph mode

3183

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3184

		       ((unsigned int) AT91C_PA30_IRQ1),	// Peripheral A

3185

		       ((unsigned int) AT91C_PA20_IRQ0) | ((unsigned int) AT91C_PA19_FIQ));	// Peripheral B

3186

3187

3188

//*----------------------------------------------------------------------------

3189

//* \fn    AT91F_TWI_CfgPMC

3190

//* \brief Enable Peripheral clock in PMC for  TWI

3191

//*----------------------------------------------------------------------------

3192

static inline void

3193

AT91F_TWI_CfgPMC (void)

3194

3195

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3196

			       ((unsigned int) 1 << AT91C_ID_TWI));

3197

3198

3199

//*----------------------------------------------------------------------------

3200

//* \fn    AT91F_TWI_CfgPIO

3201

//* \brief Configure PIO controllers to drive TWI signals

3202

//*----------------------------------------------------------------------------

3203

static inline void

3204

AT91F_TWI_CfgPIO (void)

3205

3206

  // Configure PIO controllers to periph mode

3207

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3208

		       ((unsigned int) AT91C_PA4_TWCK) | ((unsigned int) AT91C_PA3_TWD),	// Peripheral A

3209

		       0);	// Peripheral B

3210

3211

3212

//*----------------------------------------------------------------------------

3213

//* \fn    AT91F_PWMC_CH3_CfgPIO

3214

//* \brief Configure PIO controllers to drive PWMC_CH3 signals

3215

//*----------------------------------------------------------------------------

3216

static inline void

3217

AT91F_PWMC_CH3_CfgPIO (void)

3218

3219

  // Configure PIO controllers to periph mode

3220

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3221

		       0,	// Peripheral A

3222

		       ((unsigned int) AT91C_PA7_PWM3) | ((unsigned int) AT91C_PA14_PWM3));	// Peripheral B

3223

3224

3225

//*----------------------------------------------------------------------------

3226

//* \fn    AT91F_PWMC_CH2_CfgPIO

3227

//* \brief Configure PIO controllers to drive PWMC_CH2 signals

3228

//*----------------------------------------------------------------------------

3229

static inline void

3230

AT91F_PWMC_CH2_CfgPIO (void)

3231

3232

  // Configure PIO controllers to periph mode

3233

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3234

		       ((unsigned int) AT91C_PA2_PWM2),	// Peripheral A

3235

		       ((unsigned int) AT91C_PA13_PWM2) | ((unsigned int) AT91C_PA25_PWM2));	// Peripheral B

3236

3237

3238

//*----------------------------------------------------------------------------

3239

//* \fn    AT91F_PWMC_CH1_CfgPIO

3240

//* \brief Configure PIO controllers to drive PWMC_CH1 signals

3241

//*----------------------------------------------------------------------------

3242

static inline void

3243

AT91F_PWMC_CH1_CfgPIO (void)

3244

3245

  // Configure PIO controllers to periph mode

3246

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3247

		       ((unsigned int) AT91C_PA1_PWM1),	// Peripheral A

3248

		       ((unsigned int) AT91C_PA24_PWM1) | ((unsigned int) AT91C_PA12_PWM1));	// Peripheral B

3249

3250

3251

//*----------------------------------------------------------------------------

3252

//* \fn    AT91F_PWMC_CH0_CfgPIO

3253

//* \brief Configure PIO controllers to drive PWMC_CH0 signals

3254

//*----------------------------------------------------------------------------

3255

static inline void

3256

AT91F_PWMC_CH0_CfgPIO (void)

3257

3258

  // Configure PIO controllers to periph mode

3259

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3260

		       ((unsigned int) AT91C_PA0_PWM0),	// Peripheral A

3261

		       ((unsigned int) AT91C_PA23_PWM0) | ((unsigned int) AT91C_PA11_PWM0));	// Peripheral B

3262

3263

3264

//*----------------------------------------------------------------------------

3265

//* \fn    AT91F_ADC_CfgPMC

3266

//* \brief Enable Peripheral clock in PMC for  ADC

3267

//*----------------------------------------------------------------------------

3268

static inline void

3269

AT91F_ADC_CfgPMC (void)

3270

3271

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3272

			       ((unsigned int) 1 << AT91C_ID_ADC));

3273

3274

3275

//*----------------------------------------------------------------------------

3276

//* \fn    AT91F_ADC_CfgPIO

3277

//* \brief Configure PIO controllers to drive ADC signals

3278

//*----------------------------------------------------------------------------

3279

static inline void

3280

AT91F_ADC_CfgPIO (void)

3281

3282

  // Configure PIO controllers to periph mode

3283

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3284

		       0,	// Peripheral A

3285

		       ((unsigned int) AT91C_PA8_ADTRG));	// Peripheral B

3286

3287

3288

//*----------------------------------------------------------------------------

3289

//* \fn    AT91F_RTTC_CfgPMC

3290

//* \brief Enable Peripheral clock in PMC for  RTTC

3291

//*----------------------------------------------------------------------------

3292

static inline void

3293

AT91F_RTTC_CfgPMC (void)

3294

3295

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3296

			       ((unsigned int) 1 << AT91C_ID_SYS));

3297

3298

3299

//*----------------------------------------------------------------------------

3300

//* \fn    AT91F_UDP_CfgPMC

3301

//* \brief Enable Peripheral clock in PMC for  UDP

3302

//*----------------------------------------------------------------------------

3303

static inline void

3304

AT91F_UDP_CfgPMC (void)

3305

3306

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3307

			       ((unsigned int) 1 << AT91C_ID_UDP));

3308

3309

3310

//*----------------------------------------------------------------------------

3311

//* \fn    AT91F_TC0_CfgPMC

3312

//* \brief Enable Peripheral clock in PMC for  TC0

3313

//*----------------------------------------------------------------------------

3314

static inline void

3315

AT91F_TC0_CfgPMC (void)

3316

3317

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3318

			       ((unsigned int) 1 << AT91C_ID_TC0));

3319

3320

3321

//*----------------------------------------------------------------------------

3322

//* \fn    AT91F_TC0_CfgPIO

3323

//* \brief Configure PIO controllers to drive TC0 signals

3324

//*----------------------------------------------------------------------------

3325

static inline void

3326

AT91F_TC0_CfgPIO (void)

3327

3328

  // Configure PIO controllers to periph mode

3329

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3330

		       0,	// Peripheral A

3331

		       ((unsigned int) AT91C_PA0_TIOA0) | ((unsigned int) AT91C_PA4_TCLK0) | ((unsigned int) AT91C_PA1_TIOB0));	// Peripheral B

3332

3333

3334

//*----------------------------------------------------------------------------

3335

//* \fn    AT91F_TC1_CfgPMC

3336

//* \brief Enable Peripheral clock in PMC for  TC1

3337

//*----------------------------------------------------------------------------

3338

static inline void

3339

AT91F_TC1_CfgPMC (void)

3340

3341

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3342

			       ((unsigned int) 1 << AT91C_ID_TC1));

3343

3344

3345

//*----------------------------------------------------------------------------

3346

//* \fn    AT91F_TC1_CfgPIO

3347

//* \brief Configure PIO controllers to drive TC1 signals

3348

//*----------------------------------------------------------------------------

3349

static inline void

3350

AT91F_TC1_CfgPIO (void)

3351

3352

  // Configure PIO controllers to periph mode

3353

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3354

		       0,	// Peripheral A

3355

		       ((unsigned int) AT91C_PA15_TIOA1) | ((unsigned int) AT91C_PA28_TCLK1) | ((unsigned int) AT91C_PA16_TIOB1));	// Peripheral B

3356

3357

3358

//*----------------------------------------------------------------------------

3359

//* \fn    AT91F_TC2_CfgPMC

3360

//* \brief Enable Peripheral clock in PMC for  TC2

3361

//*----------------------------------------------------------------------------

3362

static inline void

3363

AT91F_TC2_CfgPMC (void)

3364

3365

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3366

			       ((unsigned int) 1 << AT91C_ID_TC2));

3367

3368

3369

//*----------------------------------------------------------------------------

3370

//* \fn    AT91F_TC2_CfgPIO

3371

//* \brief Configure PIO controllers to drive TC2 signals

3372

//*----------------------------------------------------------------------------

3373

static inline void

3374

AT91F_TC2_CfgPIO (void)

3375

3376

  // Configure PIO controllers to periph mode

3377

  AT91F_PIO_CfgPeriph (AT91C_BASE_PIOA,	// PIO controller base address

3378

		       0,	// Peripheral A

3379

		       ((unsigned int) AT91C_PA27_TIOB2) | ((unsigned int) AT91C_PA26_TIOA2) | ((unsigned int) AT91C_PA29_TCLK2));	// Peripheral B

3380

3381

3382

//*----------------------------------------------------------------------------

3383

//* \fn    AT91F_MC_CfgPMC

3384

//* \brief Enable Peripheral clock in PMC for  MC

3385

//*----------------------------------------------------------------------------

3386

static inline void

3387

AT91F_MC_CfgPMC (void)

3388

3389

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3390

			       ((unsigned int) 1 << AT91C_ID_SYS));

3391

3392

3393

//*----------------------------------------------------------------------------

3394

//* \fn    AT91F_PIOA_CfgPMC

3395

//* \brief Enable Peripheral clock in PMC for  PIOA

3396

//*----------------------------------------------------------------------------

3397

static inline void

3398

AT91F_PIOA_CfgPMC (void)

3399

3400

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3401

			       ((unsigned int) 1 << AT91C_ID_PIOA));

3402

3403

3404

//*----------------------------------------------------------------------------

3405

//* \fn    AT91F_PWMC_CfgPMC

3406

//* \brief Enable Peripheral clock in PMC for  PWMC

3407

//*----------------------------------------------------------------------------

3408

static inline void

3409

AT91F_PWMC_CfgPMC (void)

3410

3411

  AT91F_PMC_EnablePeriphClock (AT91C_BASE_PMC,	// PIO controller base address

3412

			       ((unsigned int) 1 << AT91C_ID_PWMC));

3413

3414

3415

#define __ramfunc __attribute__ ((long_call, section (".fastrun")))

3416

3417

#endif // lib_AT91SAM7

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openpcd/openpicc/os/core/ARM7_AT91SAM7S/lib_AT91SAM7.h @ master