1
|
[Project]
|
2
|
Current Flow=Generic
|
3
|
VCS=0
|
4
|
version=3
|
5
|
Current Config=compile
|
6
|
|
7
|
[Configurations]
|
8
|
compile=usbrx_vhdl
|
9
|
|
10
|
[Library]
|
11
|
usbrx_vhdl=.\usbrx_vhdl.LIB
|
12
|
|
13
|
[Settings]
|
14
|
AccessRead=0
|
15
|
AccessReadWrite=0
|
16
|
AccessACCB=0
|
17
|
AccessACCR=0
|
18
|
AccessReadWriteSLP=0
|
19
|
AccessReadTopLevel=1
|
20
|
DisableC=1
|
21
|
ENABLE_ADV_DATAFLOW=0
|
22
|
FLOW_TYPE=HDL
|
23
|
LANGUAGE=VHDL
|
24
|
REFRESH_FLOW=1
|
25
|
FAMILY=Lattice XP2
|
26
|
fileopeninsrc=1
|
27
|
fileopenfolder=C:\DVB\sr_systems\sr-usbrx\osmo-sdr\fpga\hw-v2\src\mt_toolbox
|
28
|
IMPL_TOOL=
|
29
|
SYNTH_TOOL=
|
30
|
NoWarningsSDF=0
|
31
|
SDFErrorLimit=0
|
32
|
EnableSDFErrorLimit=0
|
33
|
ChangeSDFErrorToWarning=0
|
34
|
NoTchkMsg=0
|
35
|
NoTimingChecks=0
|
36
|
HESPrepare=0
|
37
|
EnableXtrace=0
|
38
|
SplitNetVectors=0
|
39
|
StackMemorySize=32
|
40
|
RetvalMemorySize=32
|
41
|
VsimAdditionalOptions=
|
42
|
DisableVitalMsg=0
|
43
|
VitalAccel=1
|
44
|
VitalGlitches=0
|
45
|
DisableIEEEWarnings=0
|
46
|
|
47
|
[LocalVerilogSets]
|
48
|
EnableSLP=1
|
49
|
EnableDebug=0
|
50
|
|
51
|
[LocalVhdlSets]
|
52
|
CompileWithDebug=1
|
53
|
DisableVHDL87Key=0
|
54
|
EnableVHDL93Key=0
|
55
|
EnableVHDL2002Key=1
|
56
|
EnableVHDL2006Key=0
|
57
|
EnableVHDL2008Key=0
|
58
|
NetlistCompilation=1
|
59
|
Syntax RelaxLRM=0
|
60
|
MaxErrorsKey=100
|
61
|
OptimizationLevel=3
|
62
|
DisableRangeChecks=0
|
63
|
ProtectLevel=0
|
64
|
AdditionalOptions=
|
65
|
IncrementalCompilation=0
|
66
|
|
67
|
[$LibMap$]
|
68
|
usbrx_vhdl=.
|
69
|
Active_lib=
|
70
|
|
71
|
[HierarchyViewer]
|
72
|
SortInfo=u
|
73
|
HierarchyInformation=
|
74
|
ShowHide=ShowTopLevel
|
75
|
Selected=
|
76
|
|
77
|
[Folders]
|
78
|
Name3=Makefiles
|
79
|
Directory3=C:\
|
80
|
Extension3=mak
|
81
|
Name4=Memory
|
82
|
Directory4=C:\
|
83
|
Extension4=mem;mif;hex
|
84
|
Name5=Dll Libraries
|
85
|
Directory5=C:\
|
86
|
Extension5=dll
|
87
|
Name6=PDF
|
88
|
Directory6=C:\
|
89
|
Extension6=pdf
|
90
|
Name7=HTML
|
91
|
Directory7=C:\
|
92
|
Extension7=
|
93
|
|
94
|
[sdf.c.structure_con]
|
95
|
|
96
|
[sdf.ea.tb_usbrx-rtl]
|
97
|
0=src\testbench\usbrx_vhdl_usbrx_vhdl_vho.sdf| /tb_usbrx/uut, Average, No
|
98
|
|
99
|
[Groups]
|
100
|
mt_toolbox=1
|
101
|
mt_filter=1
|
102
|
usbrx=1
|
103
|
usbrx\filter=1
|
104
|
usbrx\datapath=1
|
105
|
usbrx\toplevel=1
|
106
|
testbench=1
|
107
|
|
108
|
[Files]
|
109
|
mt_toolbox/mt_toolbox.vhd=-1
|
110
|
mt_toolbox/mt_clktools.vhd=-1
|
111
|
mt_toolbox/mt_synctools.vhd=-1
|
112
|
mt_filter/mt_filter.vhd=-1
|
113
|
mt_filter/mt_fil_storage_slow.vhd=-1
|
114
|
mt_filter/mt_fil_mac_slow.vhd=-1
|
115
|
mt_filter/mt_fir_symmetric_slow.vhd=-1
|
116
|
usbrx/usbrx.vhd=-1
|
117
|
usbrx\filter/usbrx_halfband.vhd=-1
|
118
|
usbrx\datapath/usbrx_ad7357.vhd=-1
|
119
|
usbrx\datapath/usbrx_offset.vhd=-1
|
120
|
usbrx\datapath/usbrx_decimate.vhd=-1
|
121
|
usbrx\datapath/usbrx_ssc.vhd=-1
|
122
|
usbrx\toplevel/usbrx_clkgen.vhd=-1
|
123
|
usbrx\toplevel/usbrx_clkref.vhd=-1
|
124
|
usbrx\toplevel/usbrx_gpio.vhd=-1
|
125
|
usbrx\toplevel/usbrx_spi.vhd=-1
|
126
|
usbrx\toplevel/usbrx_regbank.vhd=-1
|
127
|
usbrx\toplevel/usbrx_pwm.vhd=-1
|
128
|
usbrx\toplevel/usbrx_toplevel.vhd=-1
|
129
|
testbench/tb_filter.vhd=-1
|
130
|
testbench/tb_usbrx.vhd=-1
|
131
|
|
132
|
[Files.Data]
|
133
|
.\src\mt_toolbox\mt_toolbox.vhd=VHDL Source Code
|
134
|
.\src\mt_toolbox\mt_clktools.vhd=VHDL Source Code
|
135
|
.\src\mt_toolbox\mt_synctools.vhd=VHDL Source Code
|
136
|
.\src\mt_filter\mt_filter.vhd=VHDL Source Code
|
137
|
.\src\mt_filter\mt_fil_storage_slow.vhd=VHDL Source Code
|
138
|
.\src\mt_filter\mt_fil_mac_slow.vhd=VHDL Source Code
|
139
|
.\src\mt_filter\mt_fir_symmetric_slow.vhd=VHDL Source Code
|
140
|
.\src\usbrx\usbrx.vhd=VHDL Source Code
|
141
|
.\src\usbrx\filter\usbrx_halfband.vhd=VHDL Source Code
|
142
|
.\src\usbrx\datapath\usbrx_ad7357.vhd=VHDL Source Code
|
143
|
.\src\usbrx\datapath\usbrx_offset.vhd=VHDL Source Code
|
144
|
.\src\usbrx\datapath\usbrx_decimate.vhd=VHDL Source Code
|
145
|
.\src\usbrx\datapath\usbrx_ssc.vhd=VHDL Source Code
|
146
|
.\src\usbrx\toplevel\usbrx_clkgen.vhd=VHDL Source Code
|
147
|
.\src\usbrx\toplevel\usbrx_clkref.vhd=VHDL Source Code
|
148
|
.\src\usbrx\toplevel\usbrx_gpio.vhd=VHDL Source Code
|
149
|
.\src\usbrx\toplevel\usbrx_spi.vhd=VHDL Source Code
|
150
|
.\src\usbrx\toplevel\usbrx_regbank.vhd=VHDL Source Code
|
151
|
.\src\usbrx\toplevel\usbrx_pwm.vhd=VHDL Source Code
|
152
|
.\src\usbrx\toplevel\usbrx_toplevel.vhd=VHDL Source Code
|
153
|
.\src\testbench\tb_filter.vhd=VHDL Source Code
|
154
|
.\src\testbench\tb_usbrx.vhd=VHDL Test Bench
|
155
|
|