Osmo-e1-xcvr » History » Version 20
laforge, 05/04/2018 10:35 PM
1 | 8 | laforge | {{>toc}} |
---|---|---|---|
2 | 1 | laforge | |
3 | 8 | laforge | h1. osmo-e1-xcvr |
4 | |||
5 | |||
6 | 11 | laforge | This is a simple hardware project that aims to generate a reusable module for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller projects. |
7 | 1 | laforge | |
8 | 11 | laforge | The board contains tranformers, the analog circuitry, the LIU (line interface unit), an oscillator as well as an integrated transceiver chip. |
9 | 1 | laforge | |
10 | 11 | laforge | It exposes the control interface (SPI) as well as the decoded synchronous Rx/Tx bitstreams each on a 2x5pin header. |
11 | 1 | laforge | |
12 | 11 | laforge | Framer, Multiplexer, HDLC decoder or anything like that is out-of-scope for now. The idea relaly is to provide an interface as low-level as possible. |
13 | 1 | laforge | |
14 | 11 | laforge | One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC via USB. The 2Mbps signal is very low-bandwidth, so that a pure software implementation should be absolutely no problem for todays computing power. |
15 | 8 | laforge | |
16 | |||
17 | h2. Status |
||
18 | 1 | laforge | |
19 | 11 | laforge | The project is in design phase. Initial design has finished, but needs to be reviewed. First prototype PCBs are evaluated since January 12, 2012 |
20 | 1 | laforge | |
21 | |||
22 | 8 | laforge | h2. Hardware pictures |
23 | |||
24 | |||
25 | |||
26 | h3. Bare PCB |
||
27 | |||
28 | 9 | laforge | !{width:50%}osmo-e1-xcvr-pcb.jpg! |
29 | 7 | laforge | |
30 | 8 | laforge | |
31 | h3. Populated PCB |
||
32 | |||
33 | 9 | laforge | !{width:50%}osmo-e1-xcvr.jpg! |
34 | 1 | laforge | |
35 | |||
36 | 8 | laforge | h2. Hardware Documentation |
37 | 1 | laforge | |
38 | 8 | laforge | h3. JP2: TDM interface |
39 | |||
40 | |||
41 | 1 | laforge | JP2 contains the serial TDM bitstream + clock for Rx and Tx direction. The signals are |
42 | 14 | laforge | |_.Pin|_.Name|_.Description| |
43 | |1|GND|Ground| |
||
44 | |2|nRST|low-active reset line, uC can reset the transceiver by pulling this low| |
||
45 | |3|NC|| |
||
46 | |4|LOS|Loss of Signal| |
||
47 | |5|TDN|Transmit Data Negative| |
||
48 | |6|RCLK|Receive Clock| |
||
49 | |7|TD/TDP|Transmit Data / Transmit Data Positive| |
||
50 | |8|RD/RDP|Receive Data / Receive Data Positive| |
||
51 | |9|TCLK|Transmitter Clock. Depending on JP9, this is an input into the board, or an output| |
||
52 | |10|RDN/CV|Receive Data Negative / Code Violation| |
||
53 | 1 | laforge | |
54 | 8 | laforge | h3. JP1: SPI control |
55 | |||
56 | |||
57 | 1 | laforge | This is how the external microcontroller can control the transceiver chip. |
58 | 3 | laforge | |
59 | 15 | laforge | |_.Pin|_.Name|_.Description| |
60 | |1|VCC_IN|Vcc input, board can be supplied form here if SJ2 is closed| |
||
61 | |2|GND|Ground| |
||
62 | |3|NC|Not connected| |
||
63 | |4|nINT|low-active interrupt output, when transceiver wants to interrupt uC""| |
||
64 | |5|NC|Not connected| |
||
65 | |6|NC|Not connected| |
||
66 | |7|SDO|Serial Data Out (MISO)| |
||
67 | |8|SDI|Serial Data In (MOSI)| |
||
68 | |9|SCLK|Serial Clock| |
||
69 | |10|nCS|low-active chip-select of the SPI| |
||
70 | 1 | laforge | |
71 | 8 | laforge | h3. JP9 |
72 | |||
73 | |||
74 | 2 | laforge | JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators |
75 | 1 | laforge | of 2.048 MHz and 1.544 MHz. This is required for selecting between E1 or T1/J1 mode. |
76 | |||
77 | 16 | laforge | |_.Closed|_.Frequency| |
78 | |1-2|2.048 MHz (E1) mode| |
||
79 | |2-3|1.544 MHz (T1/J1) mode| |
||
80 | 1 | laforge | |
81 | 8 | laforge | h3. JP10 |
82 | |||
83 | |||
84 | 1 | laforge | This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock. |
85 | |||
86 | 18 | laforge | |_.State|_.Meaning| |
87 | 17 | laforge | |closed|use MCLK as TCLK source, TCLK pin on JP2 is output| |
88 | |open|external circuit provides TCLK on JP2| |
||
89 | 1 | laforge | |
90 | 8 | laforge | h3. JP3 + JP4 |
91 | |||
92 | |||
93 | 1 | laforge | JP3can be used to supply power to the board. |
94 | |||
95 | 8 | laforge | h2. show me the code |
96 | |||
97 | 1 | laforge | |
98 | 12 | laforge | http://cgit.osmocom.org/osmo-e1-xcvr/ |
99 | 8 | laforge | |
100 | h2. TODO list |
||
101 | |||
102 | * hardware |
||
103 | ** make ridiculously large test pads smaller |
||
104 | ** move C1 closer to U1 VDDIO pad (19) |
||
105 | ** remove $ sign from component names |
||
106 | ** define which value C5 should use |
||
107 | ** mark pin 1 of J1 / J2 on copper + silk screen |
||
108 | ** different footprint for L1 ? value ? |
||
109 | ** JP10 is a big too close to J1 |
||
110 | 19 | laforge | * J1 is too close to J2; it's not possible to attach two standard IDC cable connectors |
111 | 8 | laforge | * software |
112 | ** implement minimal SPI driver to initialize transceiver chip |