E1 Specifications » History » Version 1
laforge, 05/04/2018 07:48 PM
1 | 1 | laforge | h1. E1 Specifications |
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3 | h2. G.702 "Digital Hierarchy Bit Rates" |
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5 | * describes the hierarchy of 64k/2048k/8448k/34368k/139264k and their T1 counterparts |
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7 | h2. G.703 "Physical/electrical characteristics of hierarchical digital interface" |
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9 | Section 11 describes the "E12" interface at 2048 kbit/s |
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11 | * Nominal bit rate: 2048 kbit/s |
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12 | * Bit rate accuracy: +/-50 ppm (+/-102.4 bit/s) |
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13 | * Code: High density bipolar of order 3 (HDB3) (a description of this code can be found in Annex A) |
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14 | * Overvoltage protection requirements: refer to [ITU-T K.20] |
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16 | The RJ45 / twisted pair interface uses 120 ohms differential/symmetric signaling with a nominal peak voltage of 3V and a nominal space voltage of 0V |
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18 | h2. G.704 "Synchronous frame structures used at 1544, 6312, 2048, 8448 and 44 736 kbit/s hierarchical levels" |
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20 | Section 2.3 specifies the basic frame structure at 2048 kbit/s |
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22 | * the basic frame consists of 256 bits, numbered 1 to 256 |
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23 | * the frame repetition rate is 8000 Hz |
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24 | * bits 1..8 of the frame have special significance, they contain the frame alignment signal (FAS) and the S-bits |
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25 | * an optional CRC-4 mechanism can be used in bit 1 of the frame, using so-called CRC-4 multiframes composed of 16 frames |
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27 | Section 5.1 specifies the interface at 2048 kbit/s carrying 64 kbit/s channels |
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29 | * FIXME |
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31 | h2. HDLC |
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33 | In the signaling timeslots (typically 64k slots, sometimes 16k sub-slots), HDLC is used for framing. It delimits the start and end of the octet and frame boundaries within the bitstream of the (sub)slot. See "wikipedia":https://en.wikipedia.org/wiki/High-Level_Data_Link_Control for a general introduction into HDLC. |
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35 | ISO/IEC 13239 specifies HDLC. |
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37 | * "ISO/IEC 13239 in Online Browsing Platform of IEC":https://www.iso.org/obp/ui/#iso:std:iso-iec:13239:en |
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38 | * "Official Homepage of ISO/IEC 13239":https://www.iso.org/standard/37010.html |