= UmTRX architecture =

The LMS6002D FPRF ICs provide analogue filtering, VGAs, VCOs and mixers etc. in addition to performing digital conversion.

DC offset and IQ balance correction is implemented in the front-end in the FPGA.

Host connection is via gigabit Ethernet and samples along with timestamps and system settings such as frequency, gain and bandwidth, are encapsulated in [http://www.vita.com/home/Specification/Specifications.html VITA Radio Transport] (VRT) packets.

Higher TX and RX sample rates are used in the front-end than in communication with the host, and half-band and CIC filters implemented in the FPGA are used to perform up/down-conversion, with amplitude correction in place pre (RX) and post (TX) filtering. This allows the frequency to be shifted within the original sample rate and without having to re-tune the LMS6002D transceiver.

After filtering, RX samples are immediately forwarded to the host by Ethernet packet router.

TX packets received from the host are buffered by a SRAM FIFO to help ensure that there are always samples to transmit.

RX samples are time-stamped and TX samples can be sent at a precise time, ensuring that TX and RX are perfectly aligned (this is critical for TDM systems).

Image(UmTRX.png,75%)

Image(FPGA_structure.png,50%)