= UmTRX architecture =

A typical SDR architecture is employed, whereby higher TX and RX sample rates are used in the front-end than in communication with the host. This is made possible by half-band and CIC filters that are implemented inside the FPGA, and which perform up/down-conversion and thereby shift the frequency within the original sample rate, with amplitude correction in place pre (RX) and post (TX) filtering.

After filtering, RX samples are stuffed into VITA Radio Transport (VRT) packets and immediately forwarded to the host by the Ethernet packet router. On the TX side, packets received from the host are first placed into a SRAM FIFO, which buffers samples so that we always have something to send. RX samples are time-stamped and TX samples can be sent at a precise time, ensuring that TX and RX are perfectly aligned (this is critical for TDM systems).

DC offset and IQ balance correction is implemented in the signal chain front-end in the FPGA.

The LMS6002D ICs provide analogue filtering, VGAs, VCOs and mixers etc. in addition to performing digital conversion.

Image(UmTRX.png,75%)

Image(FPGA_structure.png,50%)