Project

General

Profile

E1 Interface Blocks » History » Version 4

laforge, 01/13/2020 11:00 AM

1 1 laforge
{{>toc}}
2
3
h1. E1 Interface Blocks
4
5
An E1 interface is typically split into a couple of different blocks
6
7 4 laforge
This is a high-level overview of the functional blocks of a classic E1/T1 adapter, such as a E1 card supported by mISDN, DAHDI, ...:
8
{{graphviz_link()
9
digraph G {
10
  rankdir = LR;
11
  XFMR [label="Magnetics"];
12
  BTS -> XFMR [label="E1"];
13
  subgraph cluster_A {
14
    label = "Classic E1/T1 Adapter (PCI/PCIe)";
15
    XFMR -> LIU [label="E1 (HDB3)"];
16
    LIU -> TDMCTRL;
17
    TDMCTRL -> Bridge [label="Parallel Bus"];
18
  }
19
  Bridge -> CPU [label="PCI / PCIe"];
20
}
21
}}
22
23 1 laforge
h2. Transformer / Magnetics
24
25
The transformer perfrorms galvanic isolation between the wires of the line/cable and the E1 interface circuit.  Think of Ethernet, which follows the exact same principle.
26
27
h2. Line Interface Unit (LIU)
28
29
The LIU sits between the E1 controller and the magnetics
30
31
The LIU is responsible for
32
* converting the received ternary HDB3 encoding into a stream of binary bits
33
* converting to-be-transmitted binary bits into ternary HDB3 encoding
34
35
Sometimes, further functionality such as clock recovery, loopback, jitter attenuator, ... are built into the LIU.
36
37
h3. XRT59L91
38
39
An example for a very simple LIU is the "Exar XRT59L91":https://www.exar.com/ds/xrt59l91v100.pdf. It only contains
40
* Rx: receive equalizer, peak detector, LOS detector
41
* Tx: pulse shaping, output drivers
42
43
It doesn't even do any HDB3 encoding/decoding or clock recovery
44
45
h3. XRT82D20
46
47
An example for a medium complexity LIU is the "Exar XRT82D20":https://www.exar.com/ds/xrt82d20_v108_082806.pdf. It contains
48
* transmit side
49
** HDB3 encoder
50
** Tx pulse shaper for both 75 Ohms coax and 120 Ohms twisted pair
51
** line driver
52
* receiver side
53
** peak detector, data slicer, LOS detect (to digital output)
54
** data + timing recovery
55
** hdb3 decoder
56
* digital, local and remote loopback capability
57
58
Compared to the XRT59L91, the significant addition is the HDB3 en/decoders and the timing recovery.
59
60
h3. IDT82V2081
61
62
An example for an even more higher end LIU is the "IDT82V2081":https://zh.idt.com/document/dst/82v2081-datasheet. compared to the XRT82D20, it contains
63
* adaptive internal termination for rx and tx
64
* adaptive equalizer on receive side
65
* PRBS detector / generator
66
* ILBC detector / generator
67
* not only E1, but also T1 + J1 compatibility
68
* SPI or parallel bus control interface
69
70
We're using the IDT82V2081 in the osmo-e1-xcvr evaluation board.
71
72
Another example in this category is the "Dallas/Maxim DS21348":https://datasheets.maximintegrated.com/en/ds/DS21348-DS21Q348.pdf
73
74
75 2 laforge
h2. E1 Controller "framer"
76 1 laforge
77
The E1 controller is what implements
78
* frame (and multiframe) alignment
79
* CRC4 generation/verification
80
* HDLC processors for the individual timeslots
81
* interface with the host computer
82
83 2 laforge
Examples for such controllers are
84 3 laforge
* Siemens/Infineon FALC/DualFALCQuadFALC/OctalFALC, LIU + Framer + HDLC + parallel bus interface)
85
** used in many BTS/telecom equipment, but also in Digium E1/T1 cards
86
** *obsolete/EOL*
87
* "CologneChip HFC-E1":http://www.colognechip.com/hfc-e1.pdf (LIU + Framer + HDLC + DMA engine with PCI bus interface)
88
** used in PCI cards we used for original OpenBSC development with Siemens BS-11 BTS
89
** supported by mISDN
90 2 laforge
* "Exar XRT86VL30":https://www.exar.com/ds/86vl30t1_v101_121809.pdf (LIU + Framer + HDLC + DMA engine with intel/motorola parallel bus)
91
* "Dallas/Maxim DS26521":https://datasheets.maximintegrated.com/en/ds/DS26521.pdf (SPI or parallel bus, TDM Backplane)
Add picture from clipboard (Maximum size: 48.8 MB)