E1 Interface Blocks » History » Version 4
laforge, 01/13/2020 11:00 AM
1 | 1 | laforge | {{>toc}} |
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2 | |||
3 | h1. E1 Interface Blocks |
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4 | |||
5 | An E1 interface is typically split into a couple of different blocks |
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7 | 4 | laforge | This is a high-level overview of the functional blocks of a classic E1/T1 adapter, such as a E1 card supported by mISDN, DAHDI, ...: |
8 | {{graphviz_link() |
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9 | digraph G { |
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10 | rankdir = LR; |
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11 | XFMR [label="Magnetics"]; |
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12 | BTS -> XFMR [label="E1"]; |
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13 | subgraph cluster_A { |
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14 | label = "Classic E1/T1 Adapter (PCI/PCIe)"; |
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15 | XFMR -> LIU [label="E1 (HDB3)"]; |
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16 | LIU -> TDMCTRL; |
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17 | TDMCTRL -> Bridge [label="Parallel Bus"]; |
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18 | } |
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19 | Bridge -> CPU [label="PCI / PCIe"]; |
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20 | } |
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21 | }} |
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22 | |||
23 | 1 | laforge | h2. Transformer / Magnetics |
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25 | The transformer perfrorms galvanic isolation between the wires of the line/cable and the E1 interface circuit. Think of Ethernet, which follows the exact same principle. |
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26 | |||
27 | h2. Line Interface Unit (LIU) |
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28 | |||
29 | The LIU sits between the E1 controller and the magnetics |
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30 | |||
31 | The LIU is responsible for |
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32 | * converting the received ternary HDB3 encoding into a stream of binary bits |
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33 | * converting to-be-transmitted binary bits into ternary HDB3 encoding |
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34 | |||
35 | Sometimes, further functionality such as clock recovery, loopback, jitter attenuator, ... are built into the LIU. |
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36 | |||
37 | h3. XRT59L91 |
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38 | |||
39 | An example for a very simple LIU is the "Exar XRT59L91":https://www.exar.com/ds/xrt59l91v100.pdf. It only contains |
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40 | * Rx: receive equalizer, peak detector, LOS detector |
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41 | * Tx: pulse shaping, output drivers |
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42 | |||
43 | It doesn't even do any HDB3 encoding/decoding or clock recovery |
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44 | |||
45 | h3. XRT82D20 |
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46 | |||
47 | An example for a medium complexity LIU is the "Exar XRT82D20":https://www.exar.com/ds/xrt82d20_v108_082806.pdf. It contains |
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48 | * transmit side |
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49 | ** HDB3 encoder |
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50 | ** Tx pulse shaper for both 75 Ohms coax and 120 Ohms twisted pair |
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51 | ** line driver |
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52 | * receiver side |
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53 | ** peak detector, data slicer, LOS detect (to digital output) |
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54 | ** data + timing recovery |
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55 | ** hdb3 decoder |
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56 | * digital, local and remote loopback capability |
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57 | |||
58 | Compared to the XRT59L91, the significant addition is the HDB3 en/decoders and the timing recovery. |
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59 | |||
60 | h3. IDT82V2081 |
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61 | |||
62 | An example for an even more higher end LIU is the "IDT82V2081":https://zh.idt.com/document/dst/82v2081-datasheet. compared to the XRT82D20, it contains |
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63 | * adaptive internal termination for rx and tx |
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64 | * adaptive equalizer on receive side |
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65 | * PRBS detector / generator |
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66 | * ILBC detector / generator |
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67 | * not only E1, but also T1 + J1 compatibility |
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68 | * SPI or parallel bus control interface |
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69 | |||
70 | We're using the IDT82V2081 in the osmo-e1-xcvr evaluation board. |
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71 | |||
72 | Another example in this category is the "Dallas/Maxim DS21348":https://datasheets.maximintegrated.com/en/ds/DS21348-DS21Q348.pdf |
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74 | |||
75 | 2 | laforge | h2. E1 Controller "framer" |
76 | 1 | laforge | |
77 | The E1 controller is what implements |
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78 | * frame (and multiframe) alignment |
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79 | * CRC4 generation/verification |
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80 | * HDLC processors for the individual timeslots |
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81 | * interface with the host computer |
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82 | |||
83 | 2 | laforge | Examples for such controllers are |
84 | 3 | laforge | * Siemens/Infineon FALC/DualFALCQuadFALC/OctalFALC, LIU + Framer + HDLC + parallel bus interface) |
85 | ** used in many BTS/telecom equipment, but also in Digium E1/T1 cards |
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86 | ** *obsolete/EOL* |
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87 | * "CologneChip HFC-E1":http://www.colognechip.com/hfc-e1.pdf (LIU + Framer + HDLC + DMA engine with PCI bus interface) |
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88 | ** used in PCI cards we used for original OpenBSC development with Siemens BS-11 BTS |
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89 | ** supported by mISDN |
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90 | 2 | laforge | * "Exar XRT86VL30":https://www.exar.com/ds/86vl30t1_v101_121809.pdf (LIU + Framer + HDLC + DMA engine with intel/motorola parallel bus) |
91 | * "Dallas/Maxim DS26521":https://datasheets.maximintegrated.com/en/ds/DS26521.pdf (SPI or parallel bus, TDM Backplane) |