GsmDevelBoardGsmDevelBoardFPGA » History » Version 3
laforge, 02/19/2016 10:48 PM
1 | 1 | laforge | = The FPGA on the GSM Development Board = |
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2 | |||
3 | == Functional Blocks == |
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4 | |||
5 | 3 | laforge | === CLK13GEN === |
6 | The 13MHz master clock generator. We feed the 26MHz clock as generated by the [wiki:TRF6151] VCTCXO into the FPGA and want a 13MHz clock as result. |
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7 | |||
8 | 1 | laforge | === TPU === |
9 | 3 | laforge | The purpose of the TPU is to pre-configure certain events to happen synchronous to a certain time. ''Time'' in this context means |
10 | a clock ticking at a rate of CLK_QBIT. |
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11 | 1 | laforge | |
12 | 3 | laforge | ==== TPU CLK_QBIT ==== |
13 | CLK_QBIT = CLK_13M/12 equals 923.1ns, which is a quarter of a GSM bit. |
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14 | |||
15 | This clock has to be generated internally by a divider. |
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16 | |||
17 | ==== Actual TPU ==== |
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18 | |||
19 | In the TI DBB, the TPU is a micro-programmable engine with an instruction set of 5 instructions. |
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20 | |||
21 | Each instruction takes four phases (FETCH, STORE, DECODE, EXECUTE). As all of the phases have to complete in CLC_QBIT, |
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22 | the engine is clocked at four times this clock, i.e. CLK_13M/3. |
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23 | |||
24 | We don't really care how many phases/stages the engine has. We simply need something that we can program to execute an event at a scheduled time. |
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25 | |||
26 | ==== TPU Requirements ==== |
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27 | |||
28 | 1 | laforge | The TPU needs to drive the [wiki:TimeSerialPort Time Serial Port] for the [wiki:TWL3025] and [wiki:TRF6151], as well as some parallel I/O lines. |
29 | |||
30 | 3 | laforge | * serial output |
31 | * CLK13M is the global 13MHz clock generated by CLK13GEN. |
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32 | * As CLK13GEN already exports this from the FPGA, no need for the TPU to export it again |
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33 | * TRF6151:STROBE -- the strobe signal for the [wiki:TRF6151] TSP |
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34 | * TWL3025:TEN -- the TSP ENable signal for the [wiki:TWL3025] TSP |
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35 | * TSP_DO -- the TSP Data Out signal, connected to TWL3025:TDR and TRF6151:DATA |
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36 | |||
37 | * parallel output |
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38 | * TSPACT0 -- connected to the [wiki:TRF6151]:RESETz signal |
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39 | * TSPACT1 -- connected to the [wiki:ASM4532]:VC2 signal |
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40 | * TSPACT2 -- connected to the [wiki:ASM4532]:VC1 signal |
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41 | * TSPACT3 -- connected to the [wiki:RF3166]:BAND_SELECT signal |
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42 | * TSPACT4 -- connected to the [wiki:ASM4532]:VC3 signal |
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43 | * TSPACT9 -- connected to the [wiki:RF3166]:TX_ENABLE signal |
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44 | |||
45 | 1 | laforge | ==== TSP of TRF6151 ==== |
46 | |||
47 | The TSP to the TRF6151 uses three wires: |
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48 | * CLOCK (regular CLK_13M) |
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49 | * STROBE (generated by TPU) |
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50 | * DATA (provided by TPU at falling edge of CLOCK, TRF samples data at rising edge of CLOCK) |
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51 | |||
52 | 3 | laforge | See [wiki:Rita] for a more detailed description of the TSP timings required. |
53 | 1 | laforge | |
54 | ==== TSP of TWL3025 ==== |
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55 | |||
56 | The TSP of the TWL3025 usese three wires: |
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57 | * CLOCK (regular CLK_13M), the TSL3025 derives an internal CLK6.5 signal of half the clock rate and uses it for the TSP) |
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58 | * nTEN (TSP ENable) |
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59 | * TDR (sampled by TWL3025 at rising edge of CLK6.5) |
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60 | |||
61 | 3 | laforge | See [wiki:Iota] for a more detailed description of the TSP timings required. |