GsmDevelBoardGsmDevelBoardFPGA » History » Version 1
laforge, 02/19/2016 10:48 PM
1 | 1 | laforge | = The FPGA on the GSM Development Board = |
---|---|---|---|
2 | |||
3 | == Functional Blocks == |
||
4 | |||
5 | === TPU === |
||
6 | |||
7 | The TPU needs to drive the [wiki:TimeSerialPort Time Serial Port] for the [wiki:TWL3025] and [wiki:TRF6151], as well as some parallel I/O lines. |
||
8 | |||
9 | ==== TSP of TRF6151 ==== |
||
10 | |||
11 | The TSP to the TRF6151 uses three wires: |
||
12 | * CLOCK (regular CLK_13M) |
||
13 | * STROBE (generated by TPU) |
||
14 | * DATA (provided by TPU at falling edge of CLOCK, TRF samples data at rising edge of CLOCK) |
||
15 | |||
16 | [[Image(Rita:trf6151_serial_1.png)]] |
||
17 | |||
18 | [[Image(Rita:trf6151_serial_2.png)]] |
||
19 | |||
20 | ==== TSP of TWL3025 ==== |
||
21 | |||
22 | The TSP of the TWL3025 usese three wires: |
||
23 | * CLOCK (regular CLK_13M), the TSL3025 derives an internal CLK6.5 signal of half the clock rate and uses it for the TSP) |
||
24 | * nTEN (TSP ENable) |
||
25 | * TDR (sampled by TWL3025 at rising edge of CLK6.5) |
||
26 | |||
27 | The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: |
||
28 | * CLK_13M is applied continuously to TSL3025 |
||
29 | * nTEN is in default state of high (inactive) |
||
30 | * internal CLK6.5 is in default state low |
||
31 | * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge |
||
32 | * next CLK13M falling edge starts first CLK6.5 rising edge |
||
33 | * every falling edge of CLK13M toggles CLK6.5 |
||
34 | * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) |
||
35 | * 7 bits are transferred during seven rising edges of CLK6.5 |
||
36 | * TEN stays asserted for 1 CLK13M period after last bit is transferred |
||
37 | * TEN needs to be released before next CLK13M rising edge to prevent another transfer |
||
38 | |||
39 | [[Image(wiki:Iota/twl3025_tsp_serial.png)]] |