GsmDevelBoard » History » Version 8
laforge, 02/19/2016 10:48 PM
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1 | 8 | laforge | [[PageOutline]] |
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2 | 3 | laforge | = Our GSM Development Board = |
3 | 1 | laforge | |
4 | 3 | laforge | The idea is simple: |
5 | * We start with the Openmoko Calypso/Iota/Rita design |
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6 | * We replace the actual digital baseband chip (Calypso) with a normal Blackfin DSP |
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7 | 1 | laforge | |
8 | 5 | laforge | The block diagram looks something like this: |
9 | 1 | laforge | |
10 | 5 | laforge | [[Image(gsmdevboard-block.png)]] |
11 | 1 | laforge | |
12 | 7 | laforge | == Components == |
13 | |||
14 | === BF537 Blackfind DSP === |
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15 | |||
16 | === Xilinx Spartan-3E FPGA === |
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17 | |||
18 | The [wiki:GsmDevelBoard/FPGA] will host the following building blocks |
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19 | * [wiki:GsmDevelBoard/FPGA TPU Interface] |
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20 | * [wiki:GsmDevelBoard/FPGA 13MHz clock generation] |
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21 | |||
22 | 1 | laforge | == Internal Interfaces == |
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24 | 7 | laforge | Each of those interfaces is connected to the Blackfin+Spartan3E module. |
25 | |||
26 | We have a dedicated wiki page about the signals that need to be connected between RF board and DSP: [wiki:GsmDevelBoard/SignalsBetweenRFandDSP] |
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27 | 1 | laforge | |
28 | === TWL3025 BSP === |
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29 | |||
30 | 6 | laforge | The [wiki:BasebandSerialPort Baseband serial Port] is a SPI port with read/write access to all TWL3025 internal registers. However, in case of downlink Rx operation, the burst |
31 | 1 | laforge | data is transferred over this port (which needs 8.66Mbps of the 13Mbps bandwidth). It is clocked by CLK13M |
32 | |||
33 | This typically connects to the Calypso BSP. |
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34 | |||
35 | === TWL3025 USP === |
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36 | |||
37 | 6 | laforge | The [wiki:MicrocontrollerSerialPort Microcontroller Serial Port] is a generic SPI port for read/write to all TWL3025 internal registers. It is clocked by CLK13M |
38 | 1 | laforge | |
39 | === TWL3025 TSP === |
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40 | |||
41 | 6 | laforge | The [wiki:TimeSerialPort Time Serial Port] is clocked by CLK13M/2 and is a pure input port, i.e. a Frame and a Data-In line are sufficient. |
42 | 1 | laforge | |
43 | This typically connects to the Calypso TPU. |
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44 | |||
45 | This interface is used for sequencing the Rx/Tx operation of the baseband interface. |
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46 | |||
47 | === TRF6151C TSP === |
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48 | |||
49 | This is a serial interface with strobe (not chip select). |
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50 | |||
51 | It is mostly used to configure the PLL, PGA Gain and power of the transceiver. |
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52 | |||
53 | This typically connects to the Calypso TSP/TPU |
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54 | 3 | laforge | |
55 | |||
56 | == Requirements == |
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57 | |||
58 | This is an overview of the different applications for a GSM Devel Board and their requirements |
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59 | |||
60 | === Requirements for the GSM MS side === |
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61 | |||
62 | * transmit and receive in one TS every frame |
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63 | * retune Rx and Tx according to hopping sequence for every frame |
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64 | * synchronize carrier clock, bitclock and frame with BTS |
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65 | |||
66 | === Requirements for a GSM scanner === |
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67 | |||
68 | * two independent receivers, one on MS-Rx, the other on BTS-Rx side |
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69 | * ability to start decoding at some point (PCH/AGCH/SDCCH) and then follow a given hopping sequence (MAIO) for one TCH |
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70 | * ability to decrypt A51/A52 with user-provided Kc |
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71 | * Jammer: possibly transmitting interference in the Tx slices of the victim |
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72 | * synchronize carrier clock, bitclock and frame with BTS |
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73 | |||
74 | ==== Possible implementation ==== |
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75 | |||
76 | * two TRF6151 in pure Rx configuration |
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77 | * one for MS-Rx side |
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78 | * other one for MS-Tx side |
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79 | * two TWL3025 in pure Rx configuration |
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80 | * both TWL3025 BSP permanently in downlink mode (I/Q samples) |
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81 | * we get 2*( 2*16*270k) bps serial samples (7.33Mbps) input signal |
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82 | * connect those two serial sample streams to CPU+DSP (blackfin?) |
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83 | * forward demodulated/decoded samples to PC |
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84 | |||
85 | === Requirements for a GSM BTS === |
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86 | |||
87 | * tune MS-Rx side to MS-Tx frequency |
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88 | * tune MS-Tx side to MS-Rx frequency |
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89 | * continuous Rx and Tx in all timeslots on one ARFCN |
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90 | * ability to determine timing advance of Uplink frames |
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91 | |||
92 | ==== Possible implementation ==== |
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93 | |||
94 | * Use two independent TRF6151 frontends one for uplink, one for downlink |
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95 | * First TRF6151 will generate 26MHz and respect AFC from TWL3025 |
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96 | * Second TRF6151 will use 'external VTXCO' configuration from 26MHz clock |