| 1 |
8a863d16
|
(no author)
|
/* Register definitions for Philips CL RC632 RFID Reader IC
|
| 2 |
|
|
*
|
| 3 |
|
|
* (C) 2005 Harald Welte <laforge@gnumonks.org>
|
| 4 |
|
|
*
|
| 5 |
|
|
* Licensed under GNU General Public License, Version 2
|
| 6 |
|
|
*/
|
| 7 |
|
|
|
| 8 |
|
|
#ifndef _CLRC632_H
|
| 9 |
|
|
#define _CLRC632_H
|
| 10 |
|
|
|
| 11 |
|
|
enum rc632_registers {
|
| 12 |
|
|
RC632_REG_PAGE0 = 0x00,
|
| 13 |
|
|
RC632_REG_COMMAND = 0x01,
|
| 14 |
|
|
RC632_REG_FIFO_DATA = 0x02,
|
| 15 |
|
|
RC632_REG_PRIMARY_STATUS = 0x03,
|
| 16 |
|
|
RC632_REG_FIFO_LENGTH = 0x04,
|
| 17 |
|
|
RC632_REG_SECONDARY_STATUS = 0x05,
|
| 18 |
|
|
RC632_REG_INTERRUPT_EN = 0x06,
|
| 19 |
|
|
RC632_REG_INTERRUPT_RQ = 0x07,
|
| 20 |
|
|
|
| 21 |
|
|
RC632_REG_PAGE1 = 0x08,
|
| 22 |
|
|
RC632_REG_CONTROL = 0x09,
|
| 23 |
|
|
RC632_REG_ERROR_FLAG = 0x0a,
|
| 24 |
|
|
RC632_REG_COLL_POS = 0x0b,
|
| 25 |
|
|
RC632_REG_TIMER_VALUE = 0x0c,
|
| 26 |
|
|
RC632_REG_CRC_RESULT_LSB = 0x0d,
|
| 27 |
|
|
RC632_REG_CRC_RESULT_MSB = 0x0e,
|
| 28 |
|
|
RC632_REG_BIT_FRAMING = 0x0f,
|
| 29 |
|
|
|
| 30 |
|
|
RC632_REG_PAGE2 = 0x10,
|
| 31 |
|
|
RC632_REG_TX_CONTROL = 0x11,
|
| 32 |
|
|
RC632_REG_CW_CONDUCTANCE = 0x12,
|
| 33 |
|
|
RC632_REG_MOD_CONDUCTANCE = 0x13,
|
| 34 |
|
|
RC632_REG_CODER_CONTROL = 0x14,
|
| 35 |
|
|
RC632_REG_MOD_WIDTH = 0x15,
|
| 36 |
|
|
RC632_REG_MOD_WIDTH_SOF = 0x16,
|
| 37 |
|
|
RC632_REG_TYPE_B_FRAMING = 0x17,
|
| 38 |
|
|
|
| 39 |
|
|
RC632_REG_PAGE3 = 0x18,
|
| 40 |
|
|
RC632_REG_RX_CONTROL1 = 0x19,
|
| 41 |
|
|
RC632_REG_DECODER_CONTROL = 0x1a,
|
| 42 |
|
|
RC632_REG_BIT_PHASE = 0x1b,
|
| 43 |
|
|
RC632_REG_RX_THRESHOLD = 0x1c,
|
| 44 |
|
|
RC632_REG_BPSK_DEM_CONTROL = 0x1d,
|
| 45 |
|
|
RC632_REG_RX_CONTROL2 = 0x1e,
|
| 46 |
|
|
RC632_REG_CLOCK_Q_CONTROL = 0x1f,
|
| 47 |
|
|
|
| 48 |
|
|
RC632_REG_PAGE4 = 0x20,
|
| 49 |
|
|
RC632_REG_RX_WAIT = 0x21,
|
| 50 |
|
|
RC632_REG_CHANNEL_REDUNDANCY = 0x22,
|
| 51 |
|
|
RC632_REG_CRC_PRESET_LSB = 0x23,
|
| 52 |
|
|
RC632_REG_CRC_PRESET_MSB = 0x24,
|
| 53 |
|
|
RC632_REG_TIME_SLOT_PERIOD = 0x25,
|
| 54 |
|
|
RC632_REG_MFOUT_SELECT = 0x26,
|
| 55 |
|
|
RC632_REG_PRESET_27 = 0x27,
|
| 56 |
|
|
|
| 57 |
|
|
RC632_REG_PAGE5 = 0x28,
|
| 58 |
|
|
RC632_REG_FIFO_LEVEL = 0x29,
|
| 59 |
|
|
RC632_REG_TIMER_CLOCK = 0x2a,
|
| 60 |
|
|
RC632_REG_TIMER_CONTROL = 0x2b,
|
| 61 |
|
|
RC632_REG_TIMER_RELOAD = 0x2c,
|
| 62 |
|
|
RC632_REG_IRQ_PIN_CONFIG = 0x2d,
|
| 63 |
|
|
RC632_REG_PRESET_2E = 0x2e,
|
| 64 |
|
|
RC632_REG_PRESET_2F = 0x2f,
|
| 65 |
|
|
|
| 66 |
|
|
RC632_REG_PAGE6 = 0x30,
|
| 67 |
|
|
|
| 68 |
|
|
RC632_REG_PAGE7 = 0x38,
|
| 69 |
|
|
RC632_REG_TEST_ANA_SELECT = 0x3a,
|
| 70 |
|
|
RC632_REG_TEST_DIGI_SELECT = 0x3d,
|
| 71 |
|
|
};
|
| 72 |
|
|
|
| 73 |
2a0d99ee
|
laforge
|
enum rc632_reg_status {
|
| 74 |
|
|
RC632_STAT_LOALERT = 0x01,
|
| 75 |
|
|
RC632_STAT_HIALERT = 0x02,
|
| 76 |
64a0ace8
|
laforge
|
RC632_STAT_ERR = 0x04,
|
| 77 |
|
|
RC632_STAT_IRQ = 0x08,
|
| 78 |
2a0d99ee
|
laforge
|
#define RC632_STAT_MODEM_MASK 0x70
|
| 79 |
|
|
RC632_STAT_MODEM_IDLE = 0x00,
|
| 80 |
|
|
RC632_STAT_MODEM_TXSOF = 0x10,
|
| 81 |
|
|
RC632_STAT_MODEM_TXDATA = 0x20,
|
| 82 |
|
|
RC632_STAT_MODEM_TXEOF = 0x30,
|
| 83 |
|
|
RC632_STAT_MODEM_GOTORX = 0x40,
|
| 84 |
|
|
RC632_STAT_MODEM_PREPARERX = 0x50,
|
| 85 |
|
|
RC632_STAT_MODEM_AWAITINGRX = 0x60,
|
| 86 |
|
|
RC632_STAT_MODEM_RECV = 0x70,
|
| 87 |
|
|
};
|
| 88 |
|
|
|
| 89 |
8a863d16
|
(no author)
|
enum rc632_reg_command {
|
| 90 |
|
|
RC632_CMD_IDLE = 0x00,
|
| 91 |
|
|
RC632_CMD_WRITE_E2 = 0x01,
|
| 92 |
|
|
RC632_CMD_READ_E2 = 0x03,
|
| 93 |
|
|
RC632_CMD_LOAD_CONFIG = 0x07,
|
| 94 |
|
|
RC632_CMD_LOAD_KEY_E2 = 0x0b,
|
| 95 |
|
|
RC632_CMD_AUTHENT1 = 0x0c,
|
| 96 |
|
|
RC632_CMD_CALC_CRC = 0x12,
|
| 97 |
|
|
RC632_CMD_AUTHENT2 = 0x14,
|
| 98 |
|
|
RC632_CMD_RECEIVE = 0x16,
|
| 99 |
|
|
RC632_CMD_LOAD_KEY = 0x19,
|
| 100 |
|
|
RC632_CMD_TRANSMIT = 0x1a,
|
| 101 |
|
|
RC632_CMD_TRANSCEIVE = 0x1e,
|
| 102 |
|
|
RC632_CMD_STARTUP = 0x3f,
|
| 103 |
|
|
};
|
| 104 |
|
|
|
| 105 |
|
|
enum rc632_reg_interrupt {
|
| 106 |
|
|
RC632_INT_LOALERT = 0x01,
|
| 107 |
|
|
RC632_INT_HIALERT = 0x02,
|
| 108 |
|
|
RC632_INT_IDLE = 0x04,
|
| 109 |
|
|
RC632_INT_RX = 0x08,
|
| 110 |
|
|
RC632_INT_TX = 0x10,
|
| 111 |
|
|
RC632_INT_TIMER = 0x20,
|
| 112 |
|
|
RC632_INT_SET = 0x80,
|
| 113 |
|
|
};
|
| 114 |
|
|
|
| 115 |
|
|
enum rc632_reg_control {
|
| 116 |
2a0d99ee
|
laforge
|
RC632_CONTROL_FIFO_FLUSH = 0x01,
|
| 117 |
|
|
RC632_CONTROL_TIMER_START = 0x02,
|
| 118 |
|
|
RC632_CONTROL_TIMER_STOP = 0x04,
|
| 119 |
8a863d16
|
(no author)
|
RC632_CONTROL_CRYPTO1_ON = 0x08,
|
| 120 |
|
|
RC632_CONTROL_POWERDOWN = 0x10,
|
| 121 |
2a0d99ee
|
laforge
|
RC632_CONTROL_STANDBY = 0x20,
|
| 122 |
8a863d16
|
(no author)
|
};
|
| 123 |
|
|
|
| 124 |
|
|
enum rc632_reg_error_flag {
|
| 125 |
|
|
RC632_ERR_FLAG_COL_ERR = 0x01,
|
| 126 |
|
|
RC632_ERR_FLAG_PARITY_ERR = 0x02,
|
| 127 |
|
|
RC632_ERR_FLAG_FRAMING_ERR = 0x04,
|
| 128 |
|
|
RC632_ERR_FLAG_CRC_ERR = 0x08,
|
| 129 |
|
|
RC632_ERR_FLAG_FIFO_OVERFLOW = 0x10,
|
| 130 |
|
|
RC632_ERR_FLAG_ACCESS_ERR = 0x20,
|
| 131 |
|
|
RC632_ERR_FLAG_KEY_ERR = 0x40,
|
| 132 |
|
|
};
|
| 133 |
|
|
|
| 134 |
|
|
enum rc632_reg_tx_control {
|
| 135 |
|
|
RC632_TXCTRL_TX1_RF_EN = 0x01,
|
| 136 |
|
|
RC632_TXCTRL_TX2_RF_EN = 0x02,
|
| 137 |
|
|
RC632_TXCTRL_TX2_CW = 0x04,
|
| 138 |
|
|
RC632_TXCTRL_TX2_INV = 0x08,
|
| 139 |
|
|
RC632_TXCTRL_FORCE_100_ASK = 0x10,
|
| 140 |
|
|
|
| 141 |
|
|
RC632_TXCTRL_MOD_SRC_LOW = 0x00,
|
| 142 |
|
|
RC632_TXCTRL_MOD_SRC_HIGH = 0x20,
|
| 143 |
|
|
RC632_TXCTRL_MOD_SRC_INT = 0x40,
|
| 144 |
|
|
RC632_TXCTRL_MOD_SRC_MFIN = 0x60,
|
| 145 |
|
|
};
|
| 146 |
|
|
|
| 147 |
|
|
enum rc632_reg_coder_control {
|
| 148 |
2a0d99ee
|
laforge
|
/* bit 2-0 TXCoding */
|
| 149 |
|
|
#define RC632_CDRCTRL_TXCD_MASK 0x07
|
| 150 |
8a863d16
|
(no author)
|
RC632_CDRCTRL_TXCD_NRZ = 0x00,
|
| 151 |
|
|
RC632_CDRCTRL_TXCD_14443A = 0x01,
|
| 152 |
|
|
RC632_CDRCTRL_TXCD_ICODE_STD = 0x04,
|
| 153 |
2a0d99ee
|
laforge
|
RC632_CDRCTRL_TXCD_ICODE_FAST = 0x05,
|
| 154 |
|
|
RC632_CDRCTRL_TXCD_15693_STD = 0x06,
|
| 155 |
|
|
RC632_CDRCTRL_TXCD_15693_FAST = 0x07,
|
| 156 |
8a863d16
|
(no author)
|
|
| 157 |
2a0d99ee
|
laforge
|
/* bit5-3 CoderRate*/
|
| 158 |
8a863d16
|
(no author)
|
#define RC632_CDRCTRL_RATE_MASK 0x38
|
| 159 |
|
|
RC632_CDRCTRL_RATE_848K = 0x00,
|
| 160 |
|
|
RC632_CDRCTRL_RATE_424K = 0x08,
|
| 161 |
|
|
RC632_CDRCTRL_RATE_212K = 0x10,
|
| 162 |
|
|
RC632_CDRCTRL_RATE_106K = 0x18,
|
| 163 |
|
|
RC632_CDRCTRL_RATE_14443B = 0x20,
|
| 164 |
|
|
RC632_CDRCTRL_RATE_15693 = 0x28,
|
| 165 |
|
|
RC632_CDRCTRL_RATE_ICODE_FAST = 0x30,
|
| 166 |
2a0d99ee
|
laforge
|
|
| 167 |
|
|
/* bit 7 SendOnePuls */
|
| 168 |
|
|
RC632_CDRCTRL_15693_EOF_PULSE = 0x80,
|
| 169 |
8a863d16
|
(no author)
|
};
|
| 170 |
|
|
|
| 171 |
|
|
enum rc632_erg_type_b_framing {
|
| 172 |
|
|
RC632_TBFRAMING_SOF_10L_2H = 0x00,
|
| 173 |
|
|
RC632_TBFRAMING_SOF_10L_3H = 0x01,
|
| 174 |
|
|
RC632_TBFRAMING_SOF_11L_2H = 0x02,
|
| 175 |
|
|
RC632_TBFRAMING_SOF_11L_3H = 0x03,
|
| 176 |
|
|
|
| 177 |
|
|
RC632_TBFRAMING_EOF_10 = 0x00,
|
| 178 |
|
|
RC632_TBFRAMING_EOF_11 = 0x20,
|
| 179 |
|
|
|
| 180 |
|
|
RC632_TBFRAMING_NO_TX_SOF = 0x80,
|
| 181 |
|
|
RC632_TBFRAMING_NO_TX_EOF = 0x40,
|
| 182 |
|
|
};
|
| 183 |
|
|
#define RC632_TBFRAMING_SPACE_SHIFT 2
|
| 184 |
|
|
#define RC632_TBFRAMING_SPACE_MASK 7
|
| 185 |
|
|
|
| 186 |
|
|
enum rc632_reg_rx_control1 {
|
| 187 |
|
|
RC632_RXCTRL1_GAIN_20DB = 0x00,
|
| 188 |
|
|
RC632_RXCTRL1_GAIN_24DB = 0x01,
|
| 189 |
|
|
RC632_RXCTRL1_GAIN_31DB = 0x02,
|
| 190 |
|
|
RC632_RXCTRL1_GAIN_35DB = 0x03,
|
| 191 |
|
|
|
| 192 |
|
|
RC632_RXCTRL1_LP_OFF = 0x04,
|
| 193 |
|
|
RC632_RXCTRL1_ISO15693 = 0x08,
|
| 194 |
|
|
RC632_RXCTRL1_ISO14443 = 0x10,
|
| 195 |
|
|
|
| 196 |
|
|
#define RC632_RXCTRL1_SUBCP_MASK 0xe0
|
| 197 |
|
|
RC632_RXCTRL1_SUBCP_1 = 0x00,
|
| 198 |
|
|
RC632_RXCTRL1_SUBCP_2 = 0x20,
|
| 199 |
|
|
RC632_RXCTRL1_SUBCP_4 = 0x40,
|
| 200 |
|
|
RC632_RXCTRL1_SUBCP_8 = 0x60,
|
| 201 |
|
|
RC632_RXCTRL1_SUBCP_16 = 0x80,
|
| 202 |
|
|
};
|
| 203 |
|
|
|
| 204 |
|
|
enum rc632_reg_decoder_control {
|
| 205 |
|
|
RC632_DECCTRL_MANCHESTER = 0x00,
|
| 206 |
|
|
RC632_DECCTRL_BPSK = 0x01,
|
| 207 |
|
|
|
| 208 |
|
|
RC632_DECCTRL_RX_INVERT = 0x04,
|
| 209 |
|
|
|
| 210 |
|
|
RC632_DECCTRL_RXFR_ICODE = 0x00,
|
| 211 |
|
|
RC632_DECCTRL_RXFR_14443A = 0x08,
|
| 212 |
|
|
RC632_DECCTRL_RXFR_15693 = 0x10,
|
| 213 |
|
|
RC632_DECCTRL_RXFR_14443B = 0x18,
|
| 214 |
|
|
|
| 215 |
|
|
RC632_DECCTRL_ZEROAFTERCOL = 0x20,
|
| 216 |
|
|
|
| 217 |
|
|
RC632_DECCTRL_RX_MULTIPLE = 0x40,
|
| 218 |
|
|
};
|
| 219 |
|
|
|
| 220 |
|
|
enum rc632_reg_bpsk_dem_control {
|
| 221 |
|
|
RC632_BPSKD_TAUB_SHIFT = 0x00,
|
| 222 |
|
|
RC632_BPSKD_TAUB_MASK = 0x03,
|
| 223 |
|
|
|
| 224 |
|
|
RC632_BPSKD_TAUD_SHIFT = 0x02,
|
| 225 |
|
|
RC632_BPSKD_TAUD_MASK = 0x03,
|
| 226 |
|
|
|
| 227 |
|
|
RC632_BPSKD_FILTER_AMP_DETECT = 0x10,
|
| 228 |
|
|
RC632_BPSKD_NO_RX_EOF = 0x20,
|
| 229 |
|
|
RC632_BPSKD_NO_RX_EGT = 0x40,
|
| 230 |
|
|
RC632_BPSKD_NO_RX_SOF = 0x80,
|
| 231 |
|
|
};
|
| 232 |
|
|
|
| 233 |
|
|
enum rc632_reg_rx_control2 {
|
| 234 |
|
|
RC632_RXCTRL2_DECSRC_LOW = 0x00,
|
| 235 |
|
|
RC632_RXCTRL2_DECSRC_INT = 0x01,
|
| 236 |
|
|
RC632_RXCTRL2_DECSRC_SUBC_MFIN = 0x10,
|
| 237 |
|
|
RC632_RXCTRL2_DECSRC_BASE_MFIN = 0x11,
|
| 238 |
|
|
|
| 239 |
|
|
RC632_RXCTRL2_AUTO_PD = 0x40,
|
| 240 |
|
|
RC632_RXCTRL2_CLK_I = 0x80,
|
| 241 |
|
|
RC632_RXCTRL2_CLK_Q = 0x00,
|
| 242 |
|
|
};
|
| 243 |
|
|
|
| 244 |
|
|
enum rc632_reg_channel_redundancy {
|
| 245 |
|
|
RC632_CR_PARITY_ENABLE = 0x01,
|
| 246 |
|
|
RC632_CR_PARITY_ODD = 0x02,
|
| 247 |
|
|
RC632_CR_TX_CRC_ENABLE = 0x04,
|
| 248 |
|
|
RC632_CR_RX_CRC_ENABLE = 0x08,
|
| 249 |
|
|
RC632_CR_CRC8 = 0x10,
|
| 250 |
|
|
RC632_CR_CRC3309 = 0x20,
|
| 251 |
|
|
};
|
| 252 |
|
|
|
| 253 |
5ab655eb
|
(no author)
|
enum rc632_reg_timer_control {
|
| 254 |
2a0d99ee
|
laforge
|
RC632_TMR_START_TX_BEGIN = 0x01,
|
| 255 |
|
|
RC632_TMR_START_TX_END = 0x02,
|
| 256 |
|
|
RC632_TMR_STOP_RX_BEGIN = 0x04,
|
| 257 |
|
|
RC632_TMR_STOP_RX_END = 0x08,
|
| 258 |
5ab655eb
|
(no author)
|
};
|
| 259 |
|
|
|
| 260 |
b17a2f66
|
(no author)
|
enum rc632_reg_irq_pin_cfg {
|
| 261 |
|
|
RC632_IRQCFG_CMOS = 0x01,
|
| 262 |
|
|
RC632_IRQCFG_INV = 0x02,
|
| 263 |
5ab655eb
|
(no author)
|
};
|
| 264 |
8a863d16
|
(no author)
|
|
| 265 |
2a0d99ee
|
laforge
|
enum rc632_reg_secondary_status {
|
| 266 |
|
|
RC632_SEC_ST_TMR_RUNNING = 0x80,
|
| 267 |
|
|
RC632_SEC_ST_E2_READY = 0x40,
|
| 268 |
|
|
RC632_SEC_ST_CRC_READY = 0x20,
|
| 269 |
|
|
};
|
| 270 |
8a863d16
|
(no author)
|
|
| 271 |
|
|
#endif
|
