PCIeSDR » History » Version 1
XK1ZU, 09/08/2020 10:18 PM
| 1 | 1 | XK1ZU | h1. PCIeSDR |
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| 3 | PCIeSDR boards are primarily supplied with Amarisoft solutions. |
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| 4 | The hardware exists in several variants which differ in the available bandwidth or the number of Rx / Tx ports. There is also a variant with a CPRI interface. There is available integrated GPS for precise time and frequency synchronization. Clock / PPS input and output is also available. Hardware is a closed source. The FPGA gateware comes in binary form. Drivers for the Linux system are supplied in the form of sources including build and installation script.The higher-level driver includes a DSP, a calibration stage, and the gateware update. It is in the form of a closed source dynamic library named libsdr.so. The C API for Linux / x86 is in the form of a header file libsdr.h which also serves as brief documentation. |
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| 6 | h2. PCIeSDR MIMO 2x2 card |
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| 8 | Frequency range: 70 MHz to 6.0 GHz |
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| 9 | RF bandwidth: <200 kHz to 56 MHz |
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| 10 | RF power output <10 dBm |
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| 11 | 4 SMA female (Tx1-Tx2-Rx1-Rx2) |
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| 12 | 1 SMA female (GPS antenna with DC power supply) |
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| 13 | 2 internal 5-pin connectors for inter-card time synchronization |
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| 14 | PCIe gen2 X1 |
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| 15 | Based on AD9361 / FPGA Artix7 / LiteX and the ecosystem of cores |
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| 17 | h2. PCIeSDR MIMO 4x4 card |
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| 19 | PCIe gen2 X4 |
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| 20 | Based on AD937X (JESD204B) / FPGA Artix7 / LiteX and the ecosystem of cores |
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| 23 | h2. References |
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| 25 | https://web.archive.org/web/20151027200938/http://www.amarisoft.com/document/SDR-MIMO-PCIe-Card.pdf |
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| 26 | http://enjoy-digital.fr |
