Auerswald COMmander Basic2 Electronics » History » Revision 5
Revision 4 (laforge, 02/20/2022 02:22 PM) → Revision 5/8 (laforge, 02/20/2022 02:25 PM)
h1. Auerswald COMmander Basic2 Electronics h2. Mainboard As we can see, there are the following main components: * StrongARM processor with SDRAM (2x Samsung K4S281632I-UC75) + Flash (ST NAND512W3A2BN6) ** this is where the [[Linux_on_Auerswald_Commander_Basic_2]] runs ** StrongARM peripheral: IC+ IP101A Ethernet PHY * TI TMS320VC5501 DSP with its own RAM (ISSI IS61LV641G-10TL) * Lattice LFEC1E programmable logic for interfacing with the bus/backplane * various smaller bus latches/drivers {{thumbnail(Auerswald_COMB2_mainboard1.jpg)}} {{thumbnail(Auerswald_COMB2_mainboard2.jpg)}} {{thumbnail(Auerswald_COMB2_mainboard_detail.jpg)}} h2. 8 S0 Module As can be seen clearly on the picutre, it uses the [[CologneChip_HFC|CologneChip HFC-8S]] 8-port S/T interface IC. There's a lattice glue logic chip for interfacing with the backplane bus, and the analog frontend + magnetics sections for 8 ports. Four ports have jumper blocks to change the NT/TE cross-over, while the other 4 ports are static. {{thumbnail(Auerswald_COMmander_8S0_top.jpg)}} {{thumbnail(Auerswald_COMmander_8S0_bottom.jpg)}} h2. 4 S0 Module This isba basically just a partially populated 8S0 module, using a HFC-4S chip instead of the HFC-8S. {{thumbnail(Auerswald_COMmander_4S0.jpg)}} {{thumbnail(Auerswald_COMmander_4S0_top.jpg)}} {{thumbnail(Auerswald_COMmander_4S0_bottom.jpg)}} h2. 8 a/b Module {{thumbnail(Auerswald_COMmander_8ab_top.jpg)}} {{thumbnail(Auerswald_COMmander_9ab_bottom.jpg)}} {{thumbnail(Auerswald_COMmander_8ab.jpg)}} h2. S2M Module The S2M (PRI) module is centered around an Infineon PEF2256E FALC56 chip. This is one of the most common E1 framers on the market. The glue logic for interfacing with the backplane/bus is implemented in a Xilinx CPLD. {{thumbnail(Auerswald_COMmander_S2M_top.jpg)}} {{thumbnail(Auerswald_COMmander_S2m_bottom.jpg)}}
