IcE1usb » History » Version 14
tnt, 11/03/2020 01:29 PM
typo
1 | 1 | tnt | h1. iCE40 E1 USB interface |
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3 | 7 | laforge | This page is the main entry point for the (completed!) "Software defined" E1 USB interface using the iCE40 FPGA at its core. |
4 | 1 | tnt | |
5 | h2. Architecture |
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6 | |||
7 | 2 | laforge | This approach tries to implement as much as possible inside an iCE40 FPGA |
8 | 1 | tnt | |
9 | Particularly, the iCE40 FPGA |
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10 | 13 | tnt | * contains the E1 PHY. There is no external LIU*, reducing the BOM cost significantly. Instead, the comparators of the FPGA are used to detect RX positive / negative pulses and normal CMOS drivers to generate the TX pulses. In practice, this has shown to work reliably on short E1 links of a few meters. We'd expect some problems in terms of long-haul E1 links, but those are not really the target use case here. |
11 | 7 | laforge | * contains the E1 framer, including frame alignment, CRC4 verification/generation, ... |
12 | 2 | laforge | * contains a USB softcore (no external USB PHY needed) |
13 | 13 | tnt | * contains a PicoRV32 softcore to implement USB protocol handling and to connect the E1 softcore with the USB softcore |
14 | 2 | laforge | |
15 | So all-in-all, we can build a USB-E1 interface from little more than an iCE40 FPGA and an E1 line transformer! |
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16 | |||
17 | 11 | laforge | {{graphviz_link() |
18 | digraph G { |
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19 | rankdir = LR; |
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20 | 1 | tnt | |
21 | 12 | tnt | BTS -> XFRM [label="E1"]; |
22 | 11 | laforge | Linux [label="Linux\nOsmoBSC"]; |
23 | subgraph cluster_A { |
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24 | 1 | tnt | label = "iCE40 E1 USB Interface"; |
25 | 12 | tnt | XFRM [label="Magnetics"]; |
26 | XFRM -> Comparators [label="E1 (HDB3)"]; |
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27 | 11 | laforge | |
28 | subgraph cluster_B { |
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29 | label = "iCE40 FPGA"; |
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30 | Comparators; |
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31 | Framer [label="E1 Framer\nSoftcore"]; |
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32 | RISCV [label="RISCV\nSoftcore"]; |
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33 | USB [label="USB\nSoftcore"]; |
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34 | Comparators -> Framer [label="E1 (Serial Bits)"]; |
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35 | Framer -> RISCV; |
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36 | RISCV -> USB; |
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37 | } |
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38 | } |
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39 | USB -> Linux [label="Frame-aligned raw\nbits over USB"]; |
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40 | } |
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41 | }} |
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42 | 10 | laforge | |
43 | 1 | tnt | h2. Current stack |
44 | 9 | laforge | |
45 | 13 | tnt | * The hardware for the first production version is documented in the https://git.osmocom.org/osmo-e1-hardware |
46 | * The fpga gateware and associated embedded firmware is hosted in the same git repository. Some parts are in submodules (be sure to use recursive clone) |
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47 | 2 | laforge | * The userspace daemon that handles the USB communication is hosted at: https://git.osmocom.org/osmo-e1d |
48 | 5 | laforge | * The support for this daemon interface to the rest of the cellular stack is merged in mainline [[libosmo-abis:]]. Make sure you build it with @--enable-e1d@, though. |
49 | 1 | tnt | |
50 | h2. Presentations |
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51 | |||
52 | * Talk from OsmoCon 2018 about the Software Defined E1 project as a whole : attachment:osmocon_2018_e1.pdf |
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53 | * Talk from OsmoDevCon 2019 about the iCE40 based solution specifically: attachment:osmodevcon_2019_e1.pdf |
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54 | 7 | laforge | * "video recording of the iC40 based approach / OsmoDevCon 2019":https://media.ccc.de/v/osmodevcon2019-97-software-defined-e1 |
55 | 1 | tnt | |
56 | h2. Status |
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57 | |||
58 | h3. Hardware |
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59 | |||
60 | 13 | tnt | * First proof of concept was done in 2018, based on manually wired protoboard to prove viability of the USB and E1 interface. |
61 | * Several hand-wired pre-production prototypes based on iCEbreaker and iCEbreaker-bitsy have been assembled and used successfully from late 2018 to early 2020 |
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62 | * A fully integrated single-board design with two E1 lines and a GPS-DO for E1 clock stability has been created by @tnt in August 2020. After a couple of prototypes were built and tested, a first production run was made and should be available through the sysmocom shop. |
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63 | 7 | laforge | |
64 | 13 | tnt | h4. Early Proof-of-Concept and Prototypes |
65 | 1 | tnt | |
66 | 13 | tnt | !{width:45%}proto_poc.jpg! |
67 | !{width:45%}ice40-e1.jpg! |
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68 | 1 | tnt | |
69 | h4. Pre-production Prototype |
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70 | 10 | laforge | |
71 | !{width:50%}osmo-e1-ice40.jpg! |
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72 | |||
73 | 13 | tnt | h4. Rev 1.0 production |
74 | |||
75 | !{width:45%}prod_pcb.jpg! |
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76 | !{width:45%}prod_batch.jpg! |
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77 | |||
78 | |||
79 | 7 | laforge | h3. Software |
80 | |||
81 | The full stack from gateware through firmware and host software has been tested and used in a variety of scenarios. |
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82 | |||
83 | 13 | tnt | * gateware for the FPGA and firmware for the RISC-V softcore is available from https://git.osmocom.org/osmo-e1-hardware and is buildable using the icestorm OSS toolchain |
84 | 1 | tnt | * The host software/driver is part of [[osmo-e1d:]], see the proejct page for related details. [[libosmo-abis:]] has been extended with [[osmo-e1d:]] support. |
85 | 8 | laforge | |
86 | h2. Credits |
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87 | |||
88 | 14 | tnt | The development of FPGA softcores, firmware, PCB schematics, PCB layout and osmo-e1d was done by Sylvain Munaut (@tnt). |