Iota » History » Revision 5
Revision 4 (laforge, 02/19/2016 10:48 PM) → Revision 5/13 (laforge, 02/19/2016 10:48 PM)
This is the Analog Baseband Chip TWL3025 == USP == This is the SPI-like control interface between DBB and the TWL3025 (ABB). [[Image(Iota:twl3025_usp.png)]] == TSP == The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: * CLK_13M is applied continuously to TSL3025 * nTEN is in default state of high (inactive) * internal CLK6.5 is in default state low * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge * next CLK13M falling edge starts first CLK6.5 rising edge * every falling edge of CLK13M toggles CLK6.5 * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) * 7 bits are transferred during seven rising edges of CLK6.5 * TEN stays asserted for 1 CLK13M period after last bit is transferred * TEN needs to be released before next CLK13M rising edge to prevent another transfer [[Image(Iota:twl3025_tsp_serial.png)]]