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HardwareCalypsoDSP » History » Version 7

Anonymous, 02/19/2016 10:48 PM
Details about guard bits

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[[PageOutline]]
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= The Calypso DSP =
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The DSP inside the Calypso is a TMS320c5x LEAD2 DSP core.
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The software inside the DSP is mainly mask-ROM implementing the signal processing related pary of GSM (mostly Rx side).
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== DSP Hardware ==
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=== Bus ===
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The DSP has its own address adress and data bus, independent of the ARM bus.
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There is a bridge (called RHEA bridge) interfacing the DSP with its peripherals.
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=== Clock ===
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The Clock is fed from the DPLL of the Calypso chip.
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=== Reset ===
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The Reset line of the DSP is controlled by the ARM.
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=== API RAM ===
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There's a shared memory window (8kWords, i.e. 16kByte) between the DSP and the ARM used for inter-CPU-communication
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== DSP Software ==
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=== Patches ===
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The normal phone firmware downloads patches into the DSP RAM, using the API memory.
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The DSP ROM code seems to contain some patch download program that is executed after reset.
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Patches are likely used to fix bugs and to extend features in the DSP
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=== API ===
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The API is the programming interface implemented via the API RAM.
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It consists of
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 * A double buffered (DB) Read Page (DSP->ARM direction, mostly response values)
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 * A double buffered (DB) Write Page (ARM->DSP direction, mostly commands)
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 * A non double-buffered (NDB) Page
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 * A parameter area
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Some parameters details:
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 * `ndb.d_tch_mode`
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   * bit 11: ABB model selection. `1` selects IOTA, `0` selects ???. This changes the address at which `BULDATA` register is expected.
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   * bit ![10:7] : Number of guard bits inserted before actual data when TXing burst. (actual value - 4). Max value seems to be 8 guard bit. After that the DSP code will do strange things. So setting a value of 4 will TX 4+4=8 guard bits and so will be `11111111000xxxxx...`. The `1` are guard bits, then 3 x `0` of tail, then the data.
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=== Timing ===
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The timing we know so far is for single-slot operation (i.e. only one of the 8 timeslots is used)
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The flow of events is as follows:
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 * The ARM utilizeds the DB Write page to define the set of actions (tasks) to be performed by the DSP
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  * It indicates which tasks (GSM and/or MISC) are to be executed by a field in the NDB page
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  * It indicates which of the two double buffered write pages was used in the NDB page
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 * The ARM tells the TPU to issue a FRAME interrupt at the next GSM frame
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 * When the first FRAME interrupt executes, the DSP starts to process the tasks as indicated by the ARM
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  * The DSP seems to need a setup time of 66 Quarter-bits before it receives RF samples via TSP (DSP_SETUP_TIME)
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  * The DSP receives and processes the sample data
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  * Results are stored as they are ready, using the DB Read page
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 * When the next FRAME interrupt executes, the ARM can read the results from the DB Read page.
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Those flows normally happen overlapping, i.e. after the first FRAME interrupt above, the ARM can already write
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the next set of commands to the ''other'' DB Write page.
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Of course, some more complex DSP tasks take more than one frame to complete.  The ARM code needs to know how
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many frame interrupts to wait before reading the results from the DB Read page.
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=== Tasks ===
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The DSP has a number of tasks that it can execute on behalf of the ARM.  A full list is available at [wiki:TSM30Layer1#DSPTasks]
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Please don't confuse DSP tasks with Layer1 tasks.  They are both called ''tasks'' and even use one namespace,
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but are distinctively different.  Each layer1 task (on the ARM) is using a sequence of one or multiple DSP tasks.
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==== CHECKSUM ====
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This task computes a checksum over the program code inside the DSP.  It is used to ensure that patches in combination with
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the ROM code have the desired overall result.
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The checksum task finishes after 1 frame.
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==== PM (Power Measurement) / AGC Task ====
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This task measures the received power level to control the gain of the analog Rx path.
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The ARM can specify how many measurements are to be taken (1,2 or 3).
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The number of measurements determines the execution time.
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==== FB (Frequency Burst) ====
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This task performs Frequency Burst detection/decoding in idle mode.
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This task finishes after a maximum of 13 frames.
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The first frame is "idle", and all further 12 frames are checked for frequency burst detection results in the NDB page.
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==== SB (Synchronization Burst) ====
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This task performs Synchronization Burst detection/decoding in idle mode.
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It has two wait-states ({{{C W W R}}})
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It processes 190 IQ samples and has a 50 bits training sequence search window starting at sample![39] and correlating the full 64 bits.
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(See PROM0:7C2C in DSP code for more details about demodulation)
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==== RX NB (Normal Burst - Reception) ====
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This task performs reception of Normal Bursts in both idle mode & dedicated mode. It should be called four times (for the 4 bursts) and the final data can be retreived on the fourth call response.
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It processes 150 IQ samples and has a 10 bits training sequence search window starting at sample![68] and correlating only 14 bits (bits 10 -> bit 23 of the TSC).
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(See PROM0:7C27 in DSP code for more details about demodulation)
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==== TCH_FB (Frequency Burst) ====
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This task performs Frequency Burst reading in dedicated mode.
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==== TCH_SB (Synchronization Burst) ====
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This task performs Synchronization Burst reading in dedicated mode.
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=== Data Formats ===
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==== Angle ====
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This angle indicates how far the received carrier clock deviates from our synthesized LO-based clock.
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It's measured in radians and coded in fx1.15 notation (fixed-point 16bit data type with 1 bit integral and 15bit fractional)
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==== SNR (Signal/Noise Ratio) ====
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The SNR as measured by the DSP is maesured in dB and coded in fx6.10 notation.
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==== Power ====
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The Power of a signal present at the ADC baseband input, coded  in 1/64dBm
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==== TOA (Time Of Arrival) ====
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When reading NB, this is expressed as full bits and seems to be only positive.
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