HardwareCalypso » History » Version 13
nion, 02/19/2016 10:48 PM
Name changed from Calypso to Hardware/Calypso
| 1 | 5 | laforge | [[PageOutline]] |
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| 2 | 1 | laforge | = Calypso Digital Baseband = |
| 3 | |||
| 4 | The Calypso Digital Base Band chip is a popular DBB implementation for inexpensive feature phones. |
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| 5 | |||
| 6 | 5 | laforge | The register-level manuals seem to have leaked at some point and are available from cryptome.org |
| 7 | 6 | laforge | at http://cryptome.org/ti-calypso2.pdf and http://cryptome.org/ti-calypso1.pdf |
| 8 | 5 | laforge | |
| 9 | 8 | laforge | As cryptome.org is currently suffering legal battles due to Microsoft stupidity, |
| 10 | you can use http://cryptome.quintessenz.org/mirror/ti-calypso1.pdf / http://cryptome.quintessenz.org/mirror/ti-calypso2.pdf |
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| 11 | 7 | laforge | |
| 12 | 1 | laforge | == Variants == |
| 13 | * Calypso G2 C035 |
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| 14 | * Calypso G2 C035 Lite (D751749GHH) |
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| 15 | * Like C035, only 256kBytes of internal memory |
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| 16 | 2 | laforge | |
| 17 | 12 | nion | == DSP == |
| 18 | |||
| 19 | More information on the DSP used in the Calypso DBB is available on [wiki:Hardware/CalypsoDSP]. |
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| 20 | |||
| 21 | 9 | vogelchr | == CPU == |
| 22 | |||
| 23 | The CPU embedded in the calypso chipset is a ARM7TDMI. Details documents about this CPU is available from the ARM infocenter at [http://infocenter.arm.com/help/index.jsp]. |
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| 24 | |||
| 25 | 3 | laforge | == Memory Map == |
| 26 | |||
| 27 | 4 | roh | * nCS0 0x0000'0000 ... 0x007f'ffff (C123: external NOR flash) |
| 28 | 3 | laforge | * nCS6 0x0080'0000 ... 0x00bf'ffff (internal SRAM, in case of calypso lite only 256kBytes) |
| 29 | * nCS1 0x0100'0000 ... 0x017f'ffff (C123: external SRAM) |
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| 30 | 2 | laforge | |
| 31 | == Integrated Peripherals == |
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| 32 | 7 | laforge | == Integrated Peripherals == |
| 33 | === TPU (Time Processing Unit) === |
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| 34 | * A programmable micro-engine clocked at GSM quarter-bit clock |
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| 35 | === MODEM UART === |
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| 36 | * The UART that is typically connected to a PC or the application processor in a smartphone |
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| 37 | === IRDA UART === |
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| 38 | * The UART that is either connected to IRDA or for diagnostics/programming |
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| 39 | === RIF (Radio Interface) === |
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| 40 | * Connects to the synchronous bi-directional BSP (Baseband Serial Port) |
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| 41 | === DPLL + clock block === |
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| 42 | * Generate clocks for DSP, ARM and all peripherals |
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| 43 | === GEA (GPRS Encryption Algorithm) === |
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| 44 | * Encrypts/Decrypts data according to the proprietary GEA algorithm |
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| 45 | === Watchdog timer === |
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| 46 | === Interrupt Controller === |
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| 47 | === Memory interface (SRAM/ROM) === |
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| 48 | === DMA controller === |
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| 49 | * Only usable for UART and RIF, can only DMA to small API RAM memory region |
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| 50 | === SIM card controller === |
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| 51 | * Connects to the SIM card socket in the phone |
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| 52 | === TSP controller (Time Serial Port) === |
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| 53 | * Controls the TSP, which controls the sequencing of all external peripherals like ABB, RF chip, RF PA, Antenna Switch |
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| 54 | === RTC clock === |
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| 55 | * A pretty standard realtime clock |
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| 56 | === ULPD (Ultra Low Power Device) === |
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| 57 | * Responsible for enabling the phone to go to lowest-possible power mode while IDLE, but still waking up at the right point to receive important data (like paging channel) from the BTS |
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| 58 | === I2C Master controller === |
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| 59 | * Typically connects to external peripherals like LCD (if any) |
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| 60 | 2 | laforge | |
| 61 | The controller has two oddities: |
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| 62 | 1 | laforge | * It assumes that the peripheral has an address byte. If your peripheral doesn't, you have to |
| 63 | write the first byte into the address register and not the FIFO |
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| 64 | * You cannot under-fill the FIFO, i.e. if you write 8 bytes into the 16byte deep fifo, the controller |
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| 65 | 2 | laforge | will transmit 16 bytes rather than 8. Therefore, always limit the FIFO depth to your write size! |
| 66 | 13 | nion | More details about this can be seen at [wiki:Hardware/CalypsoI2CFIFO] |
| 67 | 7 | laforge | === SPI Master controller === |
| 68 | * Connects to USP of ABB and possibly other external peripherals |
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| 69 | === TIMER1 / TIMER2 general purpose timers === |
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| 70 | 2 | laforge | The timer input clock is not mentioned in the data sheet. It seems to be 13MHz / 32, i.e. 406.25kHz |
| 71 | 7 | laforge | === PWL (PWM for Light) === |
| 72 | * connected to the screen/keypad backlight |
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| 73 | === PWT (PWM for Tones) === |
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| 74 | * connected to a buzzer for ringtone generation |
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| 75 | 10 | steve-m | |
| 76 | 11 | steve-m | === JTAG Interface === |
| 77 | |||
| 78 | The Calypso has an ARM7TDMI JTAG interface, which is exposed on phones like the Motorola [wiki:MotorolaC115 C115], [wiki:MotorolaC155 C155], [wiki:SonyEricssonJ100i Sony Ericsson J100i] and the [wiki:PirelliDPL10 Pirelli DP-L10]. |
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| 79 | With standard ARM JTAG debuggers like OpenOCD, halting the core does not work out-of-the-box, because ARM instruction 0xb needs to be executed first (which is an proprietary extension to the ARM7TDMI TAP-Controller). It is unclear what this instruction does exactly. |
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| 80 | The OpenOCD configuration file along with the corresponding svf-file is attached to this page. |
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| 81 | 10 | steve-m | |
| 82 | === Debug traces === |
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| 83 | |||
| 84 | The chip has very tiny debug traces on a small flex-pcb around the 4 sides of the chip. |
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| 85 | Which trace goes to which ball can be seen on this scan: http://www.steve-m.de/pictures/calypso_bottom.jpg |
