GsmDevelBoardGsmDevelBoardFPGA » History » Revision 3
Revision 2 (laforge, 02/19/2016 10:48 PM) → Revision 3/5 (laforge, 02/19/2016 10:48 PM)
= The FPGA on the GSM Development Board = == Functional Blocks == === CLK13GEN === The 13MHz master clock generator. We feed the 26MHz clock as generated by the [wiki:TRF6151] VCTCXO into the FPGA and want a 13MHz clock as result. === TPU === The purpose of the TPU is to pre-configure certain events to happen synchronous to a certain time. ''Time'' in this context means a clock ticking at a rate of CLK_QBIT. ==== TPU CLK_QBIT ==== CLK_QBIT = CLK_13M/12 equals 923.1ns, which is a quarter of a GSM bit. This clock has to be generated internally by a divider. ==== Actual TPU ==== In the TI DBB, the TPU is a micro-programmable engine with an instruction set of 5 instructions. Each instruction takes four phases (FETCH, STORE, DECODE, EXECUTE). As all of the phases have to complete in CLC_QBIT, the engine is clocked at four times this clock, i.e. CLK_13M/3. We don't really care how many phases/stages the engine has. We simply need something that we can program to execute an event at a scheduled time. ==== TPU Requirements ==== The TPU needs to drive the [wiki:TimeSerialPort Time Serial Port] for the [wiki:TWL3025] and [wiki:TRF6151], as well as some parallel I/O lines. * serial output * CLK13M is the global 13MHz clock generated by CLK13GEN. * As CLK13GEN already exports this from the FPGA, no need for the TPU to export it again * TRF6151:STROBE -- the strobe signal for the [wiki:TRF6151] TSP * TWL3025:TEN -- the TSP ENable signal for the [wiki:TWL3025] TSP * TSP_DO -- the TSP Data Out signal, connected to TWL3025:TDR and TRF6151:DATA * parallel output * TSPACT0 -- connected to the [wiki:TRF6151]:RESETz signal * TSPACT1 -- connected to the [wiki:ASM4532]:VC2 signal * TSPACT2 -- connected to the [wiki:ASM4532]:VC1 signal * TSPACT3 -- connected to the [wiki:RF3166]:BAND_SELECT signal * TSPACT4 -- connected to the [wiki:ASM4532]:VC3 signal * TSPACT9 -- connected to the [wiki:RF3166]:TX_ENABLE signal ==== TSP of TRF6151 ==== The TSP to the TRF6151 uses three wires: * CLOCK (regular CLK_13M) * STROBE (generated by TPU) * DATA (provided by TPU at falling edge of CLOCK, TRF samples data at rising edge of CLOCK) See [wiki:Rita] for a more detailed description of the TSP timings required. [[Image(Rita:trf6151_serial_1.png)]] [[Image(Rita:trf6151_serial_2.png)]] ==== TSP of TWL3025 ==== The TSP of the TWL3025 usese three wires: * CLOCK (regular CLK_13M), the TSL3025 derives an internal CLK6.5 signal of half the clock rate and uses it for the TSP) * nTEN (TSP ENable) * TDR (sampled by TWL3025 at rising edge of CLK6.5) See [wiki:Iota] for The CLK6.5 Signal makes things a bit more detailed description complicated than we would like. The sequence of events is something like: * CLK_13M is applied continuously to TSL3025 * nTEN is in default state of high (inactive) * internal CLK6.5 is in default state low * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge * next CLK13M falling edge starts first CLK6.5 rising edge * every falling edge of CLK13M toggles CLK6.5 * TDR is sampled at every rising edge of CLK6.5 (including the TSP timings required. first edge above) * 7 bits are transferred during seven rising edges of CLK6.5 * TEN stays asserted for 1 CLK13M period after last bit is transferred * TEN needs to be released before next CLK13M rising edge to prevent another transfer [[Image(Iota:twl3025_tsp_serial.png)]]
