this page is about some ideas that were never implemented (= vapourware)!

Our GSM Development Board

The idea is simple:
  • We start with the Openmoko Calypso/Iota/Rita design
  • We replace the actual digital baseband chip (Calypso) with a normal Blackfin DSP

The block diagram looks something like this:

Block schematics of our GSM Development board


BF537 Blackfind DSP

Xilinx Spartan-3E FPGA

The GsmDevelBoardFPGA will host the following building blocks

Internal Interfaces

Each of those interfaces is connected to the Blackfin+Spartan3E module.

We have a dedicated wiki page about the signals that need to be connected between RF board and DSP: GsmDevelBoardSignalsBetweenRFandDSP


The Baseband serial Port is a SPI port with read/write access to all TWL3025 internal registers. However, in case of downlink Rx operation, the burst
data is transferred over this port (which needs 8.66Mbps of the 13Mbps bandwidth). It is clocked by CLK13M

This typically connects to the Calypso BSP.


The Microcontroller Serial Port is a generic SPI port for read/write to all TWL3025 internal registers. It is clocked by CLK13M


The Time Serial Port is clocked by CLK13M/2 and is a pure input port, i.e. a Frame and a Data-In line are sufficient.

This typically connects to the Calypso TPU.

This interface is used for sequencing the Rx/Tx operation of the baseband interface.


This is a serial interface with strobe (not chip select).

It is mostly used to configure the PLL, PGA Gain and power of the transceiver.

This typically connects to the Calypso TSP/TPU


This is an overview of the different applications for a GSM Devel Board and their requirements

Requirements for the GSM MS side

  • transmit and receive in one TS every frame
  • retune Rx and Tx according to hopping sequence for every frame
  • synchronize carrier clock, bitclock and frame with BTS

Requirements for a GSM scanner

  • two independent receivers, one on MS-Rx, the other on BTS-Rx side
  • ability to start decoding at some point (PCH/AGCH/SDCCH) and then follow a given hopping sequence (MAIO) for one TCH
  • ability to decrypt A51/A52 with user-provided Kc
  • Jammer: possibly transmitting interference in the Tx slices of the victim
  • synchronize carrier clock, bitclock and frame with BTS

Possible implementation

  • two TRF6151 in pure Rx configuration
    • one for MS-Rx side
    • other one for MS-Tx side
  • two TWL3025 in pure Rx configuration
  • both TWL3025 BSP permanently in downlink mode (I/Q samples)
    • we get 2*( 2*16*270k) bps serial samples (7.33Mbps) input signal
  • connect those two serial sample streams to CPU+DSP (blackfin?)
  • forward demodulated/decoded samples to PC

Requirements for a GSM BTS

  • tune MS-Rx side to MS-Tx frequency
  • tune MS-Tx side to MS-Rx frequency
  • continuous Rx and Tx in all timeslots on one ARFCN
  • ability to determine timing advance of Uplink frames

Possible implementation

  • Use two independent TRF6151 frontends one for uplink, one for downlink
  • First TRF6151 will generate 26MHz and respect AFC from TWL3025
  • Second TRF6151 will use 'external VTXCO' configuration from 26MHz clock
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gsmdevboard-block.png View gsmdevboard-block.png 46.7 KB Block schematics of our GSM Development board laforge, 01/06/2010 06:02 PM

Updated by laforge about 8 years ago · 11 revisions

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