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Feature #5074

closed

restring of THT headers is rather small

Added by laforge about 3 years ago. Updated about 3 years ago.

Status:
Resolved
Priority:
Normal
Assignee:
Category:
electronics
Target version:
-
Start date:
03/13/2021
Due date:
% Done:

100%


Description

We don't populate the various 2.54mm pitch THT headers. However, in case users want to solder them to the board, I would think a larger "restring" would help solderability. The current one is rather small/thin. Not sure what our default in other designs is, mschramm?


Files

restring-THT-header2.jpg View restring-THT-header2.jpg 61.4 KB mschramm, 03/15/2021 04:22 PM
restring-THT-header1.jpg View restring-THT-header1.jpg 81.6 KB mschramm, 03/15/2021 04:22 PM
.5 annular ring.png View .5 annular ring.png 349 KB cibomahto, 03/15/2021 05:04 PM
annular-ring-05detail.png View annular-ring-05detail.png 67 KB mschramm, 03/15/2021 08:24 PM
before-back.png View before-back.png 363 KB cibomahto, 03/15/2021 09:19 PM
before-top.png View before-top.png 564 KB cibomahto, 03/15/2021 09:19 PM
after-back.png View after-back.png 336 KB cibomahto, 03/15/2021 09:19 PM
after-top.png View after-top.png 594 KB cibomahto, 03/15/2021 09:19 PM
Actions #1

Updated by mschramm about 3 years ago

Those THT header's drill diameter is 0,9mm, for them a relaxed DRC would accept restrings not smaller than 0,254mm. In the current OV design they are 0,3mm, however, if they get drilled off-center (like on mine OV, see images), they end up being smaller than needed. The switch SW1 has drills of 1mm and a restring of 0,5mm which generally leaves more freedom when soldered by hand. So 0,5mm also for the pin header would be nice if no other clearance issues arise from this: the shown wire trace in the middle of the double-row header could be moved away, but on the top side of e.g. header P4 maintaining clearance might be more work.

Alternativly, IIRC, Altium allows to define different annular ring sizes for top-mid-bottom layers, so maybe for the bottom layer, a 0,5mm setting would be nice, where for the top (as well as for the inner) layer the 0,3mm setting could remain.

Actions #2

Updated by cibomahto about 3 years ago

You're correct that it's possible to change the pad sizes on a per-layer basis. Increasing just the bottom pad size to have a .5mm annular ring requires no layout changes, so it's a quick solution.

Actions #4

Updated by mschramm about 3 years ago

OK, nice - but please ease the situation with that power wire shown there like you solved it with VBUS elsewhere.

Actions #5

Updated by cibomahto about 3 years ago

Sure, I'll move it. Is it possible to state this in a more concrete fashion, so I can make a DRC rule? Something like a minimum spacing between power-class nets and thru-hole pads? I'm assuming the goal here is to decrease the chance of an assembly error during hand soldering. It's not totally clear to me the difference between this situation and the many smaller (data) traces that are routed through the pads on that connector.

For reference, the standard clearance on the board is 6 mils.

Actions #7

Updated by mschramm about 3 years ago

works for me, thanks!

Actions #8

Updated by mschramm about 3 years ago

  • Status changed from In Progress to Resolved
  • % Done changed from 0 to 100
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